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REVIEW 2 major objections 1 minor 29 references

Memristive Devices for Computation-In-Memory

T0 review · 2 major / 1 minor · reviewed 2026-05-24 · grok-4.3

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Pith's one-line read Memristive devices enable two computation-in-memory accelerators that reduce latency, energy, and area versus conventional designs.

desk verdict The paper sketches two memristor accelerators but the performance claims rest on preliminary results that do not address device variability or other real-world non-idealities. read the letter →

arxiv 1907.07898 v1 pith:OSXRWFNE submitted 2019-07-18 cs.ET

Jintao Yu , Hoang Anh Du Nguyen , Lei Xie , Mottaqiallah Taouil , Said Hamdioui This is my paper · ORCID
classification cs.ET
keywords memristivedevicescomputation-in-memoryacceleratorsvectorprocessorautomataRRAM
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces two accelerators that perform computation inside memory using memristive devices: the Memristive Vector Processor and the RRAM Automata Processor. It positions these designs as responses to the limits of CMOS scaling and the rising demands of new applications. The central evidence consists of preliminary results showing gains in latency, energy consumption, and physical area compared with today's architectures. If accurate, the work indicates that emerging devices can sustain computing progress where scaling alone no longer suffices.

What carries the argument

Memristive devices integrated for in-memory computation within the Memristive Vector Processor and RRAM Automata Processor.

What would settle it

Fabrication and testing of the accelerators at scale that yields no measurable gains in latency, energy, or area, or that reveals major reliability failures.

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Extended reading notes

Core claim

The preliminary results of these two accelerators show significant improvement in terms of latency, energy and area as compared to today's architectures and design.

Load-bearing premise

Memristive devices can be practically fabricated, integrated, and operated in the proposed accelerator architectures at scale without major unforeseen issues in reliability or compatibility.

Editorial extensions

If this is right

  • The accelerators deliver lower latency for targeted workloads than standard designs.
  • Energy consumption drops compared with conventional architectures.
  • Physical area requirements shrink relative to today's implementations.
  • Computation-in-memory approaches can address emerging applications with tight power and speed constraints.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Success would encourage exploration of similar in-memory designs using other emerging memory technologies.
  • The reported gains might extend to workloads beyond those tested in the preliminary results.
  • Practical deployment would require solving integration questions left open by the current work.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 1 minor

Summary. The paper presents two computation-in-memory accelerators based on emerging memristive devices: the Memristive Vector Processor and the RRAM Automata Processor. It states that preliminary results of these accelerators demonstrate significant improvements in latency, energy, and area compared to today's architectures and designs.

Significance. If the performance claims can be substantiated with detailed, reproducible results that account for device non-idealities, the work could contribute to alternatives for overcoming CMOS scaling walls and the von Neumann bottleneck in data-intensive applications.

major comments (2)
  1. [Abstract] Abstract: The central claim that the accelerators show 'significant improvement in terms of latency, energy and area' rests on unspecified 'preliminary results' but supplies no data, error bars, methods, benchmarks, or verification, so the support for the performance claim cannot be evaluated.
  2. [Abstract] Abstract: The architectural proposals do not appear to include sensitivity analysis or Monte-Carlo variation sweeps; without bounding performance under realistic memristor statistics (resistance-state variability, read/write disturb, limited endurance, sneak-path effects), the reported latency/energy/area advantages may not survive translation from idealized models to fabricated devices.
minor comments (1)
  1. [Abstract] The abstract would benefit from naming the specific applications or benchmarks used for the latency/energy/area comparisons.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments. We address each major comment point-by-point below, indicating planned revisions where appropriate.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that the accelerators show 'significant improvement in terms of latency, energy and area' rests on unspecified 'preliminary results' but supplies no data, error bars, methods, benchmarks, or verification, so the support for the performance claim cannot be evaluated.

    Authors: The abstract summarizes results presented in the body of the manuscript. We agree the abstract is insufficiently specific. In revision we will expand the abstract to name the benchmarks (vector operations and automata workloads), comparison baselines, and simulation methodology, while retaining the high-level claim and pointing readers to the quantitative data and methods in the main text. revision: yes

  2. Referee: [Abstract] Abstract: The architectural proposals do not appear to include sensitivity analysis or Monte-Carlo variation sweeps; without bounding performance under realistic memristor statistics (resistance-state variability, read/write disturb, limited endurance, sneak-path effects), the reported latency/energy/area advantages may not survive translation from idealized models to fabricated devices.

    Authors: The presented results use idealized device models. We accept that this limits the strength of the claims. The revision will add a new subsection discussing the listed non-idealities, providing first-order analytical bounds on their impact and stating the modeling assumptions explicitly. Full Monte-Carlo sweeps are beyond the current scope but will be noted as future work. revision: partial

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity; architectural claims rest on preliminary results without derivations or self-referential fitting

full rationale

The paper presents two computation-in-memory accelerators (Memristive Vector Processor and RRAM Automata Processor) and states that their preliminary results show improvements in latency, energy, and area. No equations, derivations, fitted parameters, or load-bearing self-citations appear in the abstract or described content. The central claim is an empirical assertion about unspecified simulation outcomes rather than any reduction of a prediction to its own inputs by construction, imported uniqueness theorems, or ansatz smuggling. This is the normal case of a proposal paper whose validity hinges on external validation of the results, not on internal circularity.

Assumptions & free parameters 0 free parameters · 0 assumptions · 0 invented entities

Abstract provides no mathematical derivations, fitted parameters, axioms, or new postulated entities; the proposal relies on existing concepts of memristive devices without additional detail.

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Cite this review

Pith. "Pith review of Memristive Devices for Computation-In-Memory." pith.science (2026). https://pith.science/paper/OSXRWFNE

@misc{pith2026190707898,
  author       = {Pith},
  title        = {Pith review of: Memristive Devices for Computation-In-Memory},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/OSXRWFNE}},
  note         = {Machine review of arXiv:1907.07898}
}
read the original abstract

CMOS technology and its continuous scaling have made electronics and computers accessible and affordable for almost everyone on the globe; in addition, they have enabled the solutions of a wide range of societal problems and applications. Today, however, both the technology and the computer architectures are facing severe challenges/walls making them incapable of providing the demanded computing power with tight constraints. This motivates the need for the exploration of novel architectures based on new device technologies; not only to sustain the financial benefit of technology scaling, but also to develop solutions for extremely demanding emerging applications. This paper presents two computation-in-memory based accelerators making use of emerging memristive devices; they are Memristive Vector Processor and RRAM Automata Processor. The preliminary results of these two accelerators show significant improvement in terms of latency, energy and area as compared to today's architectures and design.

Figures

Figures reproduced from arXiv: 1907.07898 by the authors.

Figure 2
Figure 2. Memristive Vector Processor architecture. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Evaluation results for MVP and multicore architectures. [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Example notations for NFAs and homogeneous automata. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figures from the paper (4 more)
Figure 6
Figure 6. Figure 6: General architecture for automata processors. [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: Vector dot product operator used as switches and STEs. [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 8
Figure 8. Figure 8: Different implementations of a configurable bit. [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]
Figure 9
Figure 9. Figure 9: SPICE simulation results of a vector dot product operator. [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]

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Reference graph

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