REVIEW 4 major objections 5 minor
Negative capacitance overcomes Schottky-gate limits in GaN high-electron-mobility transistors
T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash
Pith's one-line read Adding a 1.8 nm ferroic HfO2-ZrO2 bilayer to a GaN HEMT gate raises capacitance above the Schottky value, tripling ON current and cutting gate leakage by over an order of magnitude.
desk verdict Careful GaN device data with a plausible but unproven negative-capacitance mechanism; the empirical result deserves scrutiny, and a referee should request a non-ferroelectric control before accepting the mechanism. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The central object is the ferroic HfO2-ZrO2 bilayer, ~1.8 nm thick (13 ALD cycles of ZrO2 followed by 5 cycles of HfO2), acting as a negative-capacitance element in series with the intrinsic Schottky gate capacitance $C_{g,\mathrm{Sch}}$. Negative capacitance is the regime where the ferroelectric's voltage decreases as charge increases, so in series it amplifies rather than dilutes the total capacitance: $C_{g,\mathrm{eq}} = (1/C_{\mathrm{NC}} + 1/C_{g,\mathrm{Sch}})^{-1} > C_{g,\mathrm{Sch}}$. The argument carries on the stabilization of this otherwise unstable state by the mixed ferroelectric/antiferroelectric phase coexistence, the in-situ TiN capping layer, and the resulting depolarization fields that flatten the energy landscape.
What would settle it
A GaN HEMT with an equal-thickness non-ferroelectric HfO2 gate dielectric would settle it: if that device also shows a maximum capacitance above the Schottky value, the negative-capacitance explanation is not required.
Extended reading notes
Core claim
The paper's central claim is that a ferroic negative-capacitance dielectric can push a GaN HEMT past the classical Schottky-gate limit: the measured maximum gate capacitance of the HZO-gated device is about 30 percent larger than that of an otherwise identical Schottky-gated HEMT, so $C_{g,\mathrm{eq}} > C_{g,\mathrm{Sch}}$. Because charge and drive current scale with gate capacitance, the NC device delivers nearly three times the ON current at the same intrinsic overdrive while the additional physical thickness and wide bandgap of the HZO layer reduce gate leakage by more than an order of magnitude. The paper attributes the capacitance boost to a stabilized negative capacitance in the ~1.8 nm HfO2-ZrO2 bilayer, inferred from the capacitance increase, from mixed ferroelectric orthorhombic and antiferroelectric tetragonal phases seen in TEM, and from matching capacitance-boost behavior on silicon control stacks.
Load-bearing premise
The argument depends on the assumption that the thin HZO layer is working in a stabilized negative-capacitance regime; the paper infers this from the capacitance increase and from similar silicon stacks, but it does not directly measure a negative capacitance or include a GaN control with a non-ferroelectric dielectric of the same thickness.
Editorial extensions
If this is right
- HEMT gate stacks would no longer face the classical choice between high channel charge via a Schottky gate and low leakage via a conventional dielectric: the ferroic layer gives both at once.
- The ~30 percent capacitance rise over $C_{g,\mathrm{Sch}}$ means more 2DEG charge is induced for the same gate voltage, which is why the ON current nearly triples at fixed intrinsic overdrive.
- Gate leakage falls by more than an order of magnitude because the HZO adds physical thickness and a wider bandgap without the usual series-capacitance penalty.
- The concept transfers to other 2DEG transistors, including Ga-polar GaN and III-V HEMTs, and stronger nitride ferroelectrics could enlarge the effect.
Reading between the lines
- A control device with an equal-thickness non-ferroelectric HfO2 gate would isolate whether the boost comes from the ferroic negative capacitance rather than from the bilayer's high permittivity or a measurement artifact.
- Because the HZO stack was optimized for silicon transistors, re-tuning the ZrO2:HfO2 cycle ratio, thickness, and capping stress for the GaN cap could push the capacitance and current gains beyond the roughly threefold value reported here.
- The same series-capacitance reasoning would apply to any heterostructure 2DEG transistor, but the size of the gain will depend on how the negative-capacitance layer couples to the specific cap and barrier stack, which this paper does not demonstrate.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper reports an N-polar AlGaN/GaN HEMT whose gate stack incorporates an ultrathin (~1.8 nm) ALD-grown HfO2-ZrO2 ferroelectric/antiferroelectric bilayer (HZO) capped with TiN. Compared with a Schottky-gated control fabricated on the same heterostructure, the HZO device exhibits simultaneous improvements: roughly 3x higher ON current at fixed intrinsic overdrive, lower gate leakage by more than an order of magnitude, and a gate capacitance about 30% larger than the Schottky device's. The authors attribute the capacitance and current enhancements to negative capacitance (NC) in the mixed-phase HZO layer, which they argue more than compensates for the series positive capacitance of the added dielectric. Supporting evidence includes TEM phase identification (orthorhombic ferroelectric plus tetragonal antiferroelectric), C-V data on Si MOS capacitors with the same HZO, and careful structural/electrical equivalence checks (AFM, TEM, TLM, four-probe measurements).
Significance. If the NC interpretation is correct, the paper overturns the classical series-capacitance penalty that has constrained gate dielectric integration in 2DEG-based HEMTs and would be of substantial scientific and technological interest. The empirical data collection is careful: the AFM and TEM confirm identical recess depth and epitaxial layer thicknesses, TLM shows similar sheet resistance, and the four-probe and RSD corrections give confidence in the intrinsic current comparison. The paper also transparently states that the MIS-HEMT structure was only conceptual. However, the load-bearing mechanistic claim that the HZO acts as a negative capacitance on GaN is not directly established by the present experiments; the missing non-ferroelectric control on GaN and the truncated Schottky C-V reference leave alternative explanations open. The empirical result is likely publishable, but the strong NC interpretation needs additional support or substantial reframing.
major comments (4)
- [Fig. 3D, 'Electrical Measurements' section] The Schottky C-V curve is reliable only in the narrow dissipation-factor window (D<1), which the caption indicates spans roughly -1.5 V to -0.5 V. At more forward biases the Schottky gate leaks, so the reported maximum capacitance for the control may not be the true maximum capacitance of the bare heterostructure. Because the central quantitative claim is that the NC device exceeds Cg,Sch by ~30%, the control's Cmax must be obtained without leakage truncation, for example by pulsed C-V, by a lower-leakage Schottky barrier metal, or by a MIS reference with a non-ferroelectric dielectric.
- ['Mechanism of the capacitance changes and ON current increase' and Fig. 4B] The only dielectric control measurements are on Si MOS capacitors, not on GaN HEMTs. The HZO on the GaN HEMT is separated from the 2DEG by a 4 nm GaN cap and 2.6 nm AlGaN barrier; the series capacitance and interface conditions are therefore different from the Si/SiO2 case. The Si result is plausibility evidence, not proof that the same HZO layer operates in the NC regime in the GaN stack. A GaN HEMT with an equivalent-thickness non-ferroelectric gate dielectric (e.g., 1.8 nm HfO2 without ZrO2) should be fabricated and measured to show that the capacitance and current boosts are specific to the ferroic HZO layer.
- ['Mechanism of the capacitance changes and ON current increase'] The paper uses the capacitance increase as evidence for negative capacitance and then explains the capacitance increase by negative capacitance, which is an interpretive loop. The Si MOS comparison does not break this loop for the GaN stack because it does not demonstrate negative capacitance on the GaN heterostructure. Direct evidence of negative capacitance in the GaN gate stack (e.g., transient C-V or local polarization imaging) or a falsifiable control experiment (a non-ferroelectric HfO2 gate showing reduced capacitance and current) is needed to support the central claim.
- [Supplementary fig. S9] The Schottky HEMT shows hysteresis in its bidirectional transfer sweeps while the NC HEMT is nearly hysteresis-free. This difference indicates different interface trap densities or slow trap responses between the two gate stacks. Because the stacks differ not only by the HZO layer but also by the dilute-HF surface preparation and the TiN capping layer, the higher capacitance and current could in principle result from improved interface quality rather than from negative capacitance. This confound should be explicitly discussed or controlled.
minor comments (5)
- [Fig. 1B caption] The caption correctly states that the MIS-HEMT was 'not part of the experimental investigation,' but the main text and abstract do not contain this qualification; please move it into the main text to avoid misleading readers.
- [Page 5, 'Electrical Measurements' paragraph] 'N Polar' should be hyphenated as 'N-polar' for consistency with the rest of the manuscript.
- [Fig. 3D] The caption describes the unreliable regions as 'dotted gray,' but the figure appears to use dashed lines; please make the figure and caption consistent.
- [Page 1, 'negative capacitance (NC) effect' paragraph] The term 'ferroic' is used without definition; on first use, please define it as encompassing both ferroelectric and antiferroelectric order.
- [Page 8, 'Mechanism' section, Fig. 4B description] The sentence 'the bilayer provided a similar increase in capacitance as seen before' is vague; please specify the exact comparator (SiO2 alone, HfO2 control, or both) and quantitative magnitude of the boost.
Circularity Check
No circularity found: the measured capacitance, current, and leakage comparisons are self-contained, and the NC attribution is an interpretive inference rather than a derivation loop.
full rationale
The paper's central empirical claim is a direct experimental comparison between two fabricated devices: the NC HEMT shows higher ON current, lower gate leakage, and higher measured gate capacitance than the Schottky HEMT. No parameter is fitted to the GaN data to produce these comparisons, and no fitted quantity is renamed as a prediction. The negative-capacitance explanation is an inverse inference: because a series positive capacitor would reduce the total gate capacitance, the observed increase implies that the added HZO layer contributes a negative series capacitance. That inference is consistent with the paper's stated model (C_g,eq = (1/C_d + 1/C_g,Sch)^-1), and it is not a definitional identity in which NC is defined as the capacitance boost. The paper provides an external benchmark by depositing the identical HZO on Si MOS capacitors (Fig. 4B) and showing a capacitance boost relative to SiO2 and HfO2 controls; that result is independent of the GaN device data. Heavy citation of prior NC work by the same group is present, but the present measurements and the Si control carry the argument rather than reducing it to a self-citation chain. The manuscript also explicitly discloses the two main evidence-quality limitations: the MIS-HEMT was conceptual only ('was not part of the experimental investigation in this study'), and the Schottky C-V is evaluated only where D < 1 (the dotted D > 1 regions are discarded). These are correctness risks about whether negative capacitance is the true cause of the observed boost, not circular reductions. Accordingly, no circularity step can be exhibited, and the appropriate score is 0.
Assumptions & free parameters
free parameters (1)
- ZrO2:HfO2 ALD cycle ratio =
13:5
assumptions (5)
- domain assumption Negative capacitance in a ferroelectric-dielectric series stack is stabilized by the electrostatic boundary condition and increases total capacitance.
- domain assumption A mixed ferroelectric (Pca21) and antiferroelectric (P42/nmc) phase coexistence in ultrathin HZO stabilizes negative capacitance.
- domain assumption The gate stack can be represented as a series combination of positive and negative capacitors with Cg,eq = (1/Cd + 1/Cg,Sch)^-1 and Cd negative for HZO.
- domain assumption The Schottky and NC devices are structurally identical apart from the HZO/TiN gate stack.
- domain assumption Capacitance values from C-V with dissipation factor D<1 are reliable representations of gate-channel coupling.
Cite this review
Pith. "Pith review of Negative capacitance overcomes Schottky-gate limits in GaN high-electron-mobility transistors." pith.science (2026). https://pith.science/paper/CWJP6VQQ
@misc{pith2026250616758,
author = {Pith},
title = {Pith review of: Negative capacitance overcomes Schottky-gate limits in GaN high-electron-mobility transistors},
year = {2026},
howpublished = {\url{https://pith.science/paper/CWJP6VQQ}},
note = {Machine review of arXiv:2506.16758}
}
read the original abstract
For high-electron-mobility transistors based on two-dimensional electron gas (2DEG) within a quantum well, such as those based on AlGaN/GaN heterostructure, a Schottky-gate is used to maximize the amount of charge that can be induced and thereby the current that can be achieved. However, the Schottky-gate also leads to very high leakage current through the gate electrode. Adding a conventional dielectric layer between the nitride layers and gate metal can reduce leakage; but this comes at the price of a reduced drain current. Here, we used a ferroic HfO2-ZrO2 bilayer as the gate dielectric and achieved a simultaneous increase in the ON current and decrease in the leakage current, a combination otherwise not attainable with conventional dielectrics. This approach surpasses the conventional limits of Schottky GaN transistors and provides a new pathway to improve performance in transistors based on 2DEG.
Figures
Reviewed August 15, 2026 · model on record in the stance chip above.
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