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arxiv: 2606.01776 · v1 · pith:2OBG3KFZnew · submitted 2026-06-01 · 📡 eess.SP

A 32-Channel 3.53-{μ}W Per Channel Brain-Machine Interface SoC Featuring Dual-Threshold Delta-modulation, In-Memory Spike Detection and Bi-SNN Based Motor Decoding

Ye Ke , Zhengnan Fu , Pao-Sheng Vincent Sun , An Guo , Shuai Dong , Junyi Yang , Yahan Yang , Abdelrahman B. M. Eldaly
show 3 more authors
Xin Si Leanne Chan Arindam Basu
This is my paper

Pith reviewed 2026-06-28 13:23 UTC · model grok-4.3

classification 📡 eess.SP
keywords brain-machine interfacesystem-on-chipdelta modulationspiking neural networklow-power electronicsneuromorphic computingimplantable devicemotor decoding
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The pith

A 32-channel brain-machine interface SoC achieves 3.53 μW per channel using dual-threshold delta modulation, in-memory spike detection, and a Bi-SNN decoder.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a 32-channel fully event-based implantable brain-machine interface system-on-chip fabricated in 65nm CMOS. It integrates a dual-threshold delta modulation frontend array for up to 26x data compression, an in-memory computing spike detector, and a bipolar leaky integrate-and-fire spiking neural network for on-chip motor intention decoding. The design targets the scaling challenges of high-channel-count neural sensors by reducing data volume at the frontend and performing processing on the implant. The reported performance includes 3.53 μW per channel power draw, approximately 0.62 decoding R-squared, and 0.034 mm² per-channel area. These metrics support efficient signal recording, processing, and decoding for implantable devices.

Core claim

The 32-channel fully event-based iBMI SoC integrates a dual-threshold delta modulation frontend that provides up to 26x data compression, an in-memory computing spike detector for in-pixel spike detection, and a bipolar LIF-based spiking neural network decoder for on-chip motor intention decoding, all while consuming 3.53 μW per channel and achieving ~0.62 decoding R² with a compact 0.034 mm² per-channel area in 65nm CMOS.

What carries the argument

The dual-threshold delta modulation (DTDM) frontend array combined with in-memory computing spike detection and bipolar LIF-based SNN decoder, which together form the event-based neuromorphic signal processing pipeline.

If this is right

  • The frontend achieves up to 26x data compression before any further processing.
  • Spike detection occurs in-memory within each pixel without separate digital processing steps.
  • Motor intention decoding runs on-chip using the Bi-SNN with 0.62 R² accuracy.
  • Per-channel area remains 0.034 mm² while supporting 32 channels on a single chip.
  • Total system power stays at 3.53 μW per channel for the full recording-to-decoding pipeline.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Higher channel counts become feasible without proportional increases in wireless transmission bandwidth or implant power budget.
  • The event-driven architecture may extend to other neural signal modalities beyond motor decoding.
  • In-memory spike detection could reduce latency compared to off-pixel digital detection in future scaled designs.
  • The small per-channel area leaves room for additional on-chip features such as stimulation circuitry.

Load-bearing premise

The reported power, compression ratio, and decoding accuracy were measured under conditions representative of chronic human neural recordings.

What would settle it

Power consumption, compression factor, and decoding R² measured on long-term chronic human neural data that differ substantially from the test conditions used in the paper.

Figures

Figures reproduced from arXiv: 2606.01776 by Abdelrahman B. M. Eldaly, An Guo, Arindam Basu, Junyi Yang, Leanne Chan, Pao-Sheng Vincent Sun, Shuai Dong, Xin Si, Yahan Yang, Ye Ke, Zhengnan Fu.

Figure 1
Figure 1. Figure 1: Design challenges in high-density wireless iBMIs system and proposed [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: Architecture and Circuit Implementation of the 32-Channel Chopping [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Bipolar SNN intention decoder and hardware implementation of the [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: (a) Chip Microscopic diagram, (b) Experimental setup, (c) Power [PITH_FULL_IMAGE:figures/full_fig_p003_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) AFE transfer function, (b) DTDM output and wave reconstruction [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Event rate reduction of IMC SPD. (b) Bi-SNN 2D motor decoding [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
read the original abstract

With the scaling of sensor channel counts, systems confront challenges in frontend data sensing and on-implant data processing. This work presents a 32-channel fully event-based iBMI SoC in 65nm CMOS for an efficient neuromorphic signal processing pipeline. The SoC integrates a 32-channel dual-threshold delta modulation (DTDM) frontend array that provides up to 26x data compression at the frontend, an in-memory computing (IMC) spike detector (SPD) for efficient in-pixel spike detection, and a bipolar LIF-based spiking neural network (Bi-SNN) decoder for on-chip motor intention decoding (MID). Consuming only 3.53 {\mu}W per channel and achieving ~0.62 decoding R2 with a compact 0.034 mm2 per-channel area, the chip enables high-efficiency signal recording, processing, and decoding for implantable devices.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 3 minor

Summary. The manuscript presents a 32-channel event-based implantable brain-machine interface (iBMI) SoC fabricated in 65 nm CMOS. It integrates a dual-threshold delta-modulation (DTDM) analog frontend achieving up to 26× data compression, an in-memory-computing spike detector (SPD), and a bipolar leaky-integrate-and-fire spiking neural network (Bi-SNN) for on-chip motor-intention decoding. Benchtop measurements on the fabricated die using synthetic and primate-recorded neural signals report 3.53 μW per channel, 0.034 mm² per-channel area, and ~0.62 decoding R².

Significance. If the reported power, area, and decoding metrics hold under the stated measurement conditions, the work provides a concrete, measured demonstration of a fully integrated neuromorphic pipeline that simultaneously addresses frontend compression, in-pixel detection, and on-chip decoding. The explicit tie of all figures to fabricated-silicon measurements and primate motor datasets strengthens the claim relative to simulation-only estimates common in the field.

minor comments (3)
  1. §3.2 and Fig. 7: the definition of the dual-threshold levels (V_th+ and V_th−) is given only in terms of the input-referred voltage; an explicit mapping to the comparator reference voltages used on-chip would clarify reproducibility.
  2. Table II: the R² values for the Bi-SNN are reported without the number of trials or cross-validation folds; adding these statistics would allow direct comparison with the offline baselines cited in the same table.
  3. §4.3: the power-breakdown pie chart aggregates digital and analog domains but does not separate the contribution of the IMC array from the Bi-SNN; a finer split would help readers assess scalability to higher channel counts.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the positive summary, significance assessment, and recommendation of minor revision. No major comments were provided in the report.

Circularity Check

0 steps flagged

No significant circularity

full rationale

The manuscript reports measured performance of a fabricated 65 nm CMOS SoC (power, compression ratio, area, and R² on neural datasets) obtained from benchtop tests with synthetic and recorded signals. No equations, fitted parameters, or derivations appear; the central claims are direct experimental outcomes rather than quantities obtained by construction from inputs or self-citations. The architecture description maps to metrics via explicit measurement conditions without internal reduction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No mathematical derivations, free parameters, or invented physical entities are present; the work is an empirical hardware demonstration whose claims rest on standard CMOS process assumptions and measurement practices.

pith-pipeline@v0.9.1-grok · 5746 in / 1066 out tokens · 21361 ms · 2026-06-28T13:23:13.779723+00:00 · methodology

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Reference graph

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