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Pareto-Efficient Quantum Circuit Simulation Using Tensor Contraction Deferral
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abstract
With the current rate of progress in quantum computing technologies, systems with more than 50 qubits will soon become reality. Computing ideal quantum state amplitudes for circuits of such and larger sizes is a fundamental step to assess both the correctness, performance, and scaling behavior of quantum algorithms and the fidelities of quantum devices. However, resource requirements for such calculations on classical computers grow exponentially. We show that deferring tensor contractions can extend the boundaries of what can be computed on classical systems. To demonstrate this technique, we present results obtained from a calculation of the complete set of output amplitudes of a universal random circuit with depth 27 in a 2D lattice of $7 \times 7$ qubits, and an arbitrarily selected slice of $2^{37}$ amplitudes of a universal random circuit with depth 23 in a 2D lattice of $8 \times 7$ qubits. Combining our methodology with other decomposition approaches found in the literature, we show that we can simulate $7 \times 7$-qubit random circuits to arbitrary depth by leveraging secondary storage. These calculations were thought to be impossible due to resource requirements.
Forward citations
Cited by 3 Pith papers
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Adaptive Multi-Backend Simulation of Near-Clifford Quantum Circuits via Spatial Stabilizer-Frame Partitioning
Quipu-Cut exactly simulates Clifford+T amplitudes via multilevel qubit bipartition, stabilizer-frame leaves, adaptive dense fallback, and a cost-model partition selector that beats cut-count heuristics on structured w...
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Optimizing Tensor Network Partitioning using Simulated Annealing
A simulated annealing refinement of tensor network partitionings for distributed contraction lowers estimated computational and memory cost by about 8x on average versus naive partitioning on MQT Bench circuits.
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Optimizing Memory Efficiency and Index Ordering to Simulate Quantum Circuits Using Tensor Decision Diagrams
Hardware-aware FTDD memory management plus a Path index-order heuristic bounds RAM and simulates structured circuits (e.g. QFT) up to 100 qubits, with large topology-dependent speedups.
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