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Paper Citation Record · LEDGER

Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

As of 18 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 9 inbound Pith citation observations for arXiv:1907.10701.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1907.10701 v4

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 9 of 9 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 9 of 9 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-10T23:01:04.365156Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-25T02:20:14.417068Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation d3a05b38-cbbb-4da1-aef0-b2f90d4d2bd7 · inbound

Survival of the Cheapest: Cost-Aware Hardware Adaptation for Adversarial Robustness cites this paper.

Survival of the Cheapest: Cost-Aware Hardware Adaptation for Adversarial Robustness Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 32

Resolution
verified exact
arxiv_id, observed 2026-05-23T21:15:49.399879Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-05-23T21:14:38.949892Z digest=sha256:33b87183d04d939a9689eed47c70d7ee2988e0c2b0197a737a6f601bf7f1a295

Observation 06f7c554-ae9d-429d-8c38-06ed84e54a38 · inbound

DeepLL: Considering Linear Logic for the Analysis of Deep Learning Experiments cites this paper.

DeepLL: Considering Linear Logic for the Analysis of Deep Learning Experiments Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 19

Resolution
unresolved
no resolver link, observed 2026-08-10T23:01:04.365156Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T23:01:04.365156Z digest=sha256:fce21170092e2aeac93cbbe3b9b134af9d86ef809f111bdd1bfec862b91bef3d

Observation 9e3fd83b-15ff-4cd7-8d42-2c4a41d379e5 · inbound

SMDP-Based Dynamic Batching for Improving Responsiveness and Energy Efficiency of Batch Services cites this paper.

SMDP-Based Dynamic Batching for Improving Responsiveness and Energy Efficiency of Batch Services Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 6

Resolution
unresolved
no resolver link, observed 2026-08-10T22:20:54.510900Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T22:20:54.510900Z digest=sha256:7c9da9d952c1589647eb6fb6dad468e168c97a4c3c7a15b7bfd3eebaecb91f3e

Observation 41fb8a0d-318b-45b7-95ab-53e4389c1f5e · inbound

Code Benchmarks Should Prioritize Rigor, Reliability, and Reproducibility cites this paper.

Code Benchmarks Should Prioritize Rigor, Reliability, and Reproducibility Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 26

Resolution
unresolved
no resolver link, observed 2026-08-10T19:04:25.986001Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T19:04:25.986001Z digest=sha256:5210da0aa5184eb807a5bede815222b896dc704c90cc07713b690177946f31cd

Observation ae994997-f93c-458d-884c-7d7ba2c9ebb5 · inbound

Will LLMs Scaling Hit the Wall? Breaking Barriers via Distributed Resources on Massive Edge Devices cites this paper.

Will LLMs Scaling Hit the Wall? Breaking Barriers via Distributed Resources on Massive Edge Devices Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 134

Resolution
metadata mismatch
arxiv_id, observed 2026-05-23T01:05:16.335725Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-05-23T01:03:26.037233Z digest=sha256:6d591c75d0a3f9def551cfcec046cfc8f6532118c37deddad3cd8387459c457c

Observation 1d800c68-cbaa-46d4-a8d1-43f86d82617c · inbound

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration cites this paper.

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 29

Resolution
verified exact
arxiv_id, observed 2026-05-11T06:55:58.951271Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-05-10T17:23:57.512298Z digest=sha256:c4b4fca45307bbc306c4cf27286044edf6ecdb41f15714c1c86007e1163fca88

Observation f2e2a97c-6a0a-41fe-a829-bae645295e92 · inbound

Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading cites this paper.

Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 79

Resolution
verified exact
arxiv_id, observed 2026-05-10T06:21:26.886374Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=arxiv_source observed=2026-05-10T06:20:18.479234Z digest=sha256:aeb05b2d29d9a4d7f75869dcce9c4aa80d95bd6810bc09de5400149d21769309

Observation 5f51bbeb-b4f1-49e4-baa2-91e36b6643ea · inbound

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration cites this paper.

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 52

Resolution
verified exact
arxiv_id, observed 2026-05-25T02:20:14.420124Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

source=pdf_text observed=2026-05-25T02:17:02.764223Z digest=sha256:34b1266da76324820d923a76ca3e03613bd8b0e98872a0006d1b45aede1613aa

Observation 42033959-676d-4e5b-a287-59547366981c · inbound

DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction cites this paper.

DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction Benchmarking TPU, GPU, and CPU Platforms for Deep Learning

Reference 56

Resolution
unresolved
no resolver link, observed 2026-08-01T22:14:38.679513Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-01T22:14:38.679513Z digest=sha256:9508ce6f7aa957bf3e8e17f24f325bb8dbea10a60a489a184bee3758875bc4da