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Hierarchical decoding to reduce hardware requirements for quantum computing

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arxiv 2001.11427 v1 pith:OYJGT32A submitted 2020-01-30 quant-ph cs.ITmath.IT

classification quant-phcs.ITmath.IT
keywords decoderdecodinghardwarequantumerrorlazyqubitsrequirements
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

Extensive quantum error correction is necessary in order to scale quantum hardware to the regime of practical applications. As a result, a significant amount of decoding hardware is necessary to process the colossal amount of data required to constantly detect and correct errors occurring over the millions of physical qubits driving the computation. The implementation of a recent highly optimized version of Shor's algorithm to factor a 2,048-bits integer would require more 7 TBit/s of bandwidth for the sole purpose of quantum error correction and up to 20,000 decoding units. To reduce the decoding hardware requirements, we propose a fault-tolerant quantum computing architecture based on surface codes with a cheap hard-decision decoder, the lazy decoder, combined with a sophisticated decoding unit that takes care of complex error configurations. Our design drops the decoding hardware requirements by several orders of magnitude assuming that good enough qubits are provided. Given qubits and quantum gates with a physical error rate $p=10^{-4}$, the lazy decoder drops both the bandwidth requirements and the number of decoding units by a factor 50x. Provided very good qubits with error rate $p=10^{-5}$, we obtain a 1,500x reduction in bandwidth and decoding hardware thanks to the lazy decoder. Finally, the lazy decoder can be used as a decoder accelerator. Our simulations show a 10x speed-up of the Union-Find decoder and a 50x speed-up of the Minimum Weight Perfect Matching decoder.

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Forward citations

Cited by 6 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. OpenAlex reports about 19 citations worldwide. Full citation record

  1. Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise

    quant-ph 2025-12 conditional novelty 6.0 of 10

    A cryogenic surface-code predecoder that adds spacetime-like and hook-error primitives to achieve near-MWPM logical error rates while cutting 4K-to-RT syndrome bandwidth by up to 3780x.

  2. Quantum Computing in Discrete- and Continuous-Variable Architectures

    quant-ph 2025-07 conditional novelty 6.0 of 10

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  3. Latency-Constrained Hardware-Aware Quantum Error Correction Co-Design with Adaptive Confidence-Gated Neural Decoding for the Rotated Surface Code

    quant-ph 2026-07 conditional novelty 5.0 of 10

    Confidence-gated neural decoding escalates only ~3–6% of rotated-surface-code syndromes to MWPM and raises end-to-end accuracy from 99.21% to 99.81% at d=7 under circuit-level depolarising noise.

  4. LATTE: A Decoding Architecture for Quantum Computing with Temporal and Spatial Scalability

    quant-ph 2025-09 conditional novelty 5.0 of 10

    A hybrid FPGA-CPU streaming decoder cuts syndrome transmission by over 90% and keeps feedback latency roughly constant in long surface-code memory runs.

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    quant-ph 2025-07 conditional novelty 5.0 of 10

    A modest extension of the Clique decoder, Clique_L2, corrects length-2 space error chains locally and cuts out-of-fridge decoding bandwidth by up to 18.38x under clustered noise models.

  6. Synchronization for Fault-Tolerant Quantum Computers

    quant-ph 2025-06 conditional novelty 5.0 of 10

    Active and Hybrid synchronization policies cut logical error rates by up to 2.4x and 3.4x compared to passive waiting, by distributing idle time across syndrome generation rounds.

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