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Paper Citation Record · LEDGER

On Joint Learning for Solving Placement and Routing in Chip Design

As of 15 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2111.00234.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2111.00234 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 2 of 2 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 2 of 2 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-10T21:19:09.965096Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-07T15:06:31.665459Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation a857b8c8-2d55-46bd-898e-44db6c2e8c33 · inbound

TransPlace: Transferable Circuit Global Placement via Graph Neural Network cites this paper.

TransPlace: Transferable Circuit Global Placement via Graph Neural Network On Joint Learning for Solving Placement and Routing in Chip Design

Reference 43

Resolution
unresolved
no resolver link, observed 2026-08-10T21:19:09.965096Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-10T21:19:09.965096Z digest=sha256:1f3c4136d7d73324cb75fa1a52de7b12d672107543cc430e2d5651716ff229bb

Observation ee10f170-691d-441d-85ba-0688a727a80f · inbound

DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness cites this paper.

DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness On Joint Learning for Solving Placement and Routing in Chip Design

Reference 12

Resolution
verified exact
local_arxiv, observed 2026-08-07T15:06:31.670210Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

source=pdf_text observed=2026-08-07T15:06:31.450606Z digest=sha256:515cb519492ffd18341d32012534217d6f6430324ab313395dc61294366bfe46