REVIEW 4 major objections 4 minor 41 references
DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness
T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash
Pith's one-line read DAS-MP claims that hidden dataflow between macros and standard-cell clusters, plus area- and orientation-aware fine-tuning, improves macro placement quality.
desk verdict Solid incremental EDA paper, but the headline gains are in-sample and the abstract's runtime claim is contradicted by its own Table V. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing object is a weighted, directed dataflow graph whose nodes are macro clusters and standard-cell clusters, with edge weights derived from connection bit width and, for cell-cluster-to-cell-cluster edges, the product of a constant $k$, bit width, cluster area, and cluster instance count. This graph feeds a simulated-annealing loss with three HPWL terms, $\mathrm{WL}_{m-m}$, $\mathrm{WL}_{m-c}$, and $\mathrm{WL}_{m-c-c}$, where the two-hop term is refined by a backward-feedback weight and a normalized macro-area divisor. The orientation fine-tuning step projects three vector types, $V_{\mathrm{mm}}$, $V_{\mathrm{mc}}$, and $V_{\mathrm{mcc}}$, onto x and y axes with weights $\alpha=0.55$, $\beta=0.3$, and $\gamma=0.15$, then flips each macro in the direction of larger total projection.
What would settle it
Run DAS-MP with the published hyperparameters on macro-heavy designs not used in tuning and compare HPWL, congestion overflow, and post-route WNS/TNS against the baseline dataflow-aware macro placer; if the average 7.9% HPWL improvement fails to reproduce or reverses on several of those designs, the reported gains are at least partly overfit to the benchmark suite.
Extended reading notes
Core claim
The paper's central claim, stated on its own terms, is that macro placement quality can be improved substantially by treating hidden dataflow relationships between macros and standard-cell clusters, and among cell clusters themselves, as explicit placement constraints. The proposed DAS-MP pipeline first performs threshold-limited hierarchical clustering, then extracts four types of connections: one-hop direct macro-macro connections, one-hop indirect macro-macro connections through shared cell clusters, one-hop macro-cell connections, and two-hop macro-cell-cell connections. These connections are assigned weights based on bit width, cluster area, and instance count, and are combined into the simulated-annealing loss as three HPWL terms for macro-macro, macro-cell, and macro-cell-cell flows. Two fine-tuning steps follow: a backward-feedback model scales the two-hop weight by the one-hop weight and by normalized macro area so that larger macros are pushed toward boundaries while smaller macros stay near their cell clusters, and a dataflow-vector decomposition decides each macro's orientation by projecting macro-macro, macro-cell, and macro-cell-cell vectors onto the x and y axes and flipping in the dominant direction. The paper's experiments show that this complete pipeline beats the baseline on HPWL, congestion, and post-route timing across all seven tested designs.
Load-bearing premise
The numerical weights $\alpha=0.55$, $\beta=0.3$, $\gamma=0.15$ and the constant $k$ in the cell-cluster edge weight were tuned on the same seven benchmarks, and the reported gains assume these values transfer to unseen designs.
Editorial extensions
If this is right
- Standard-cell-aware dataflow can be added to an SA macro placer without retraining, improving HPWL and congestion at the same time.
- The common practice of pushing macros to chip boundaries is not always optimal; dataflow intensity can justify interior macro locations.
- Dataflow direction can be converted automatically into macro orientation decisions, so orientation need not be a manual or brute-force step.
- Two-hop cell-cell connections carry enough placement-relevant information to influence macro placement, beyond one-hop macro-cell links.
- Because the added extraction and fine-tuning runtime stays below 1.5% of the total macro placement time, the method is cheap enough for iterative physical design flows.
Reading between the lines
- Beyond the paper's claims, the alpha/beta/gamma weights and the constant k were selected by trials on the same seven benchmarks, so a held-out test is the natural next check of whether the improvements transfer.
- The extracted macro-cell and cell-cell connections could also be exported as fence or guide constraints to downstream standard-cell placement, potentially improving the rest of the P&R flow rather than only the macro layer.
- The dataflow-vector flipping rule acts like a principal-component alignment; it might be extended to weight timing-critical connections more heavily, trading some wirelength for slack improvements.
- If the gains hold across diverse designs, dataflow extraction of this kind could become a standard preprocessing step for both analytical and RL-based macro placers, not just SA-based ones.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper proposes DAS-MP, a macro placement methodology that augments a simulated-annealing-based dataflow-aware placer with additional dataflow relationships involving standard-cell clusters. Specifically, it extracts macro-to-cell, cell-to-cell, and two-hop macro-cell-cell connections, folds them into an SA loss function, and then applies two fine-tuning steps: an area-based weight feedback model intended to reduce congestion, and a dataflow-vector-based macro flipping heuristic intended to optimize macro orientation. The paper reports experiments on seven open-source designs, comparing against TMP, RTL-MP, and Hier-RTLMP, and claims average improvements of 7.9% in HPWL, 82.5% in congestion overflow, 36.97% in WNS, and 59.44% in TNS over RTL-MP, with a runtime overhead of less than 1.5%.
Significance. If the reported results hold, the paper makes a useful and practical contribution: it extends dataflow-aware macro placement beyond macro-to-macro relationships to include macro-cell and cell-cell dataflow, and it demonstrates that two light-weight fine-tuning mechanisms can further improve placement quality. The full-flow evaluation through routing, the ablation study in Table VI separating area-based and orientation-based fine-tuning, and the detailed connection-count statistics in Table II are strengths; the paper addresses a real gap in current macro placers and is compatible with the OpenROAD flow. The main reservations concern runtime accounting, reproducibility of the tuned weights, and the clarity of the timing/power notation, as detailed below.
major comments (4)
- [Section VII-F and Table V] The abstract's claim of 'less than a 1.5% runtime overhead' is contradicted by the paper's own Table V. The average total runtime of DAS-MP (DE+FT) is reported as 208.71 s versus 66.99 s for RTL-MP, a 3.12x increase (the text in Section VII-F says 3.21x, which is also inconsistent). The 1.38% figure in Fig. 12(a) is the fraction of DAS-MP's own total runtime spent on dataflow extraction and fine-tuning, not the overhead relative to RTL-MP. Please correct the abstract and Section VII-F, and report the end-to-end runtime ratio as a headline number instead of the share of runtime.
- [Section VII-A, Eq. 13, Eq. 4] The headline quality gains are in-sample estimates. The weights alpha=0.55, beta=0.3, and gamma=0.15 in Eq. 13 were 'determined based on multiple trials across various design scales,' and the seven benchmarks were selected after 'extensive experiments'; no held-out design, cross-validation, seed variation, or error bars are provided. In addition, the constant k in Eq. 4 is never given a numerical value or a selection procedure, so the two-hop weight w2 in Eq. 5 is not reproducible from the manuscript. Please add an out-of-sample evaluation (for example, leave-one-benchmark-out or a held-out design), report sensitivity of the results to alpha, beta, gamma, and k, and state the value of k.
- [Section VII-E and Table IV] The notation for 'improvement' in the timing and power table is internally inconsistent. The text states that a positive 'improvement' in WNS/TNS denotes degradation, yet the 'Avg. Improv.*' row marks DAS-MP (DE+FT) as 36.97% and 59.44% with upward arrows while the individual rows show WNS and TNS moving toward zero, which is an improvement. The power and area entries are also labeled with downward arrows even though the accompanying text says power increases by 2.24% and area by 1.3%. Please define 'improvement' with one consistent convention, make the arrows match that convention, and recompute the average row accordingly.
- [Section IV-B and Algorithm 1] The indirect macro-macro extraction in Algorithm 1 appears to add virtual connections for every shared cell cluster or shared cell instance, but the text in Section IV-B identifies the exclusion of clock, reset, and other common high-fanout signals as a key challenge. No filtering step is visible in Algorithm 1 or described in the surrounding text. If such signals are not excluded, the proposed indirect macro-macro connections will be created between all macros sharing these signals, and the strengths w_i in Eq. 2 will be dominated by spurious common signals. Please describe how common signals are filtered, or state explicitly that they are absent from the data structures used in Algorithm 1.
minor comments (4)
- [Eq. 1] The text says 'wx is a weight factor defined by dataflow bit width,' but Eq. 1 uses w0 and w1; please make the notation consistent.
- [Table V] The column headers for the two DAS-MP (DE+FT) subcolumns are ambiguous; please label them as 'optimized M-C-C extraction' and 'total with flipping,' and use a single consistent multiplier in the average row (3.12x, not 3.21x).
- [Section VI-A, Eq. 6 and Eq. 8] The transition from loss = w1*w2 in Eq. 6 to loss = sqrt(w1*w2)/A' in Eq. 8 is not motivated; a sentence explaining the role of the square root would improve reproducibility.
- [Section VII-B] Table II reports counts of unique connections but no run-to-run variation for the SA-based placement; please state the number of seeds or the variance of the HPWL results reported in Tables III and IV.
Circularity Check
No significant circularity: the claimed gains are measured by an external OpenROAD P&R flow on external benchmarks; in-sample tuning of α/β/γ is a generalization caveat, not a circular reduction.
full rationale
The paper's central claim is an empirical one: DAS-MP improves HPWL, congestion, WNS, and TNS relative to RTL-MP. The evaluation is conducted through the full OpenROAD placement-and-routing flow on seven external benchmarks, with RTL-MP, Hier-RTLMP, and TMP as external baselines. The loss function in Eq. 5 is a weighted sum of macro-related HPWL terms, but the reported HPWL and PPA numbers come from the downstream P&R flow, so the improvement is not identical to the optimized objective by construction. The dataflow-extraction component is taken from the authors' prior work [11], and the flipping mechanism overlaps prior work [34]; these are self-citations, but the current paper re-implements and evaluates the combined system, so the result does not reduce to an unverified citation. The most notable weakness is in-sample tuning: Section VI-B3 states that α=0.55, β=0.3, γ=0.15 were 'determined based on multiple trials across various design scales,' and Section VII-A states the seven benchmarks were chosen after extensive experiments. This means the reported average improvements are on the same designs used for hyperparameter selection, and the constant k in Eq. 4 is not given, so the results may not generalize. However, that is a statistical-validity and reproducibility concern rather than a circular derivation: no equation is defined in terms of the quantity it is supposed to predict, and the final metrics are externally computed. The self-citations and in-sample tuning are sufficient for a modest score but do not make the central claim equivalent to its inputs.
Assumptions & free parameters
free parameters (4)
- alpha, beta, gamma (VT projection weights) =
0.55, 0.30, 0.15
- k (cell-cluster to cell-cluster weighting constant) =
unspecified
- two-hop scope cutoff =
2 hops
- clustering threshold =
not reported
assumptions (5)
- domain assumption Standard cell clusters can be treated as pseudo-macros whose placement influences macro placement.
- domain assumption Bitwidth of connections is the correct proxy for dataflow importance.
- domain assumption Larger macros should be pushed to the chip boundary and smaller macros kept near cell clusters.
- ad hoc to paper Macro orientation is limited to 0 and 180 degree flips, and flipping can be guided by the sign of projected dataflow vectors.
- standard math Simulated annealing with sequence-pair representation finds a near-optimum of the weighted HPWL loss.
invented entities (1)
-
Virtual indirect macro-macro connections
Cite this review
Pith. "Pith review of DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness." pith.science (2026). https://pith.science/paper/X2EDRENC
@misc{pith2026250516445,
author = {Pith},
title = {Pith review of: DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness},
year = {2026},
howpublished = {\url{https://pith.science/paper/X2EDRENC}},
note = {Machine review of arXiv:2505.16445}
}
read the original abstract
Dataflow is a critical yet underexplored factor in automatic macro placement, which is becoming increasingly important for developing intelligent design automation techniques that minimize reliance on manual adjustments and reduce design iterations. Existing macro or mixed-size placers with dataflow awareness primarily focus on intrinsic relationships among macros, overlooking the crucial influence of standard cell clusters on macro placement. To address this, we propose DAS-MP, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enhance dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow information. By integrating enhanced dataflow awareness into placement constraints and applying these fine-tuning steps, the proposed approach achieves an average 7.9% improvement in half-perimeter wirelength (HPWL) across multiple widely used benchmark designs compared to a state-of-the-art dataflow-aware macro placer. Additionally, it significantly improves congestion, reducing overflow by an average of 82.5%, and achieves improvements of 36.97% in Worst Negative Slack (WNS) and 59.44% in Total Negative Slack (TNS). The approach also maintains efficient runtime throughout the entire placement process, incurring less than a 1.5% runtime overhead. These results show that the proposed dataflow-driven methodology, combined with the fine-tuning steps, provides an effective foundation for macro placement and can be seamlessly integrated into existing design flows to enhance placement quality.
Figures
Figures from the paper (7 more)
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Reviewed August 7, 2026 · model on record in the stance chip above.
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