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Plated-Through-Hole Via Design Specifications for 112G Serial Links

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arxiv 2304.01913 v1 pith:THXLAHW5 submitted 2023-01-17 cs.NI eess.SP

Michael J. Degerstrom , Chad M. Smutzer , Richard B. Ericson , Clifton R Haider , Barry K. Gilbert This is my paper · ORCID
classification cs.NIeess.SP
keywords designlinksviasbandwidthboardhighlayer-countpam-4
verification ladder T0 review T1 audit T2 compute T3 formal

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An earlier study of a high layer-count test board using plated-through-hole (PTH) vias and a limited quantity of laser vias was shown to be capable of supporting 112 Gb/s PAM-4 links (or equivalent signaling having 28 GHz (Nyquist) bandwidth). This original board design was then rebuilt using a different fabricator, and the test results revealed a significant decrease in the bandwidth of the vias. These results led to the development of a set of design specifications that PCB vendors can easily validate, which will ensure that the use of high layer-count boards with PTH technology are viable for emerging 112 Gb/s PAM-4 links.

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