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Defense against ML-based Power Side-channel Attacks on DNN Accelerators with Adversarial Attacks

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arxiv 2312.04035 v1 pith:DUNXFLW3 submitted 2023-12-07 cs.CR

classification cs.CR
keywords acceleratorsattackslearningside-channeladversaryaiashielddefensenoise
verification ladder T0 review T1 audit T2 compute T3 formal
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Artificial Intelligence (AI) hardware accelerators have been widely adopted to enhance the efficiency of deep learning applications. However, they also raise security concerns regarding their vulnerability to power side-channel attacks (SCA). In these attacks, the adversary exploits unintended communication channels to infer sensitive information processed by the accelerator, posing significant privacy and copyright risks to the models. Advanced machine learning algorithms are further employed to facilitate the side-channel analysis and exacerbate the privacy issue of AI accelerators. Traditional defense strategies naively inject execution noise to the runtime of AI models, which inevitably introduce large overheads. In this paper, we present AIAShield, a novel defense methodology to safeguard FPGA-based AI accelerators and mitigate model extraction threats via power-based SCAs. The key insight of AIAShield is to leverage the prominent adversarial attack technique from the machine learning community to craft delicate noise, which can significantly obfuscate the adversary's side-channel observation while incurring minimal overhead to the execution of the protected model. At the hardware level, we design a new module based on ring oscillators to achieve fine-grained noise generation. At the algorithm level, we repurpose Neural Architecture Search to worsen the adversary's extraction results. Extensive experiments on the Nvidia Deep Learning Accelerator (NVDLA) demonstrate that AIAShield outperforms existing solutions with excellent transferability.

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Hardware-Agnostic Modeling of Quantum Side-Channel Leakage via Conditional Dynamics and Learning from Full Correlation Data

    quant-ph 2026-02 reject novelty 4.0 of 10

    For a controlled-rotation probe, gate-sequence leakage is predicted to peak at θ*(k)=2 arcsin(√(2/(k+2))), but the paper provides neither a derivation of the envelope nor the experimental data supporting the prediction.

  2. Securing Deep Learning Hardware: A Survey of Side-Channel Vulnerabilities and Countermeasures

    cs.CR 2026-07 accept novelty 3.0 of 10

    Hardware side-channel attacks can recover deep-learning model architecture, parameters and inputs; this survey taxonomizes the leaks, attacks and countermeasures.

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