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Escaping Local Optima in Global Placement

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arxiv 2402.18311 v1 pith:ZWEQGNGK submitted 2024-02-28 cs.LG cs.NE

classification cs.LGcs.NE
keywords placementlocaloptimadreamplaceframeworkglobalmethodsperformance
verification ladder T0 review T1 audit T2 compute T3 formal
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Placement is crucial in the physical design, as it greatly affects power, performance, and area metrics. Recent advancements in analytical methods, such as DREAMPlace, have demonstrated impressive performance in global placement. However, DREAMPlace has some limitations, e.g., may not guarantee legalizable placements under the same settings, leading to fragile and unpredictable results. This paper highlights the main issue as being stuck in local optima, and proposes a hybrid optimization framework to efficiently escape the local optima, by perturbing the placement result iteratively. The proposed framework achieves significant improvements compared to state-of-the-art methods on two popular benchmarks.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

    cs.LG 2025-10 conditional novelty 5.0 of 10

    BBOPlace-Bench is a unified benchmark for black-box optimization of chip placement, where evolutionary algorithms under mask-guided and hyperparameter formulations beat analytical and RL baselines on wirelength metrics.

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