Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
As of 14 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 4 inbound Pith citation observations for arXiv:2405.17378.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-14T06:32:32.682623+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-10T23:11:12.565591Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-10T10:49:56.163880Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation dbe70cb5-e447-43a0-b808-d2e944474e8c · inbound
AGON: Automated Design Framework for Customizing Processors from ISA Documents cites this paper.
AGON: Automated Design Framework for Customizing Processors from ISA Documents RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
Reference 15
- Resolution
- unresolved
- no resolver link, observed 2026-08-10T23:11:12.565591Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 21b84afa-e999-46d3-bac9-982d151e82df · inbound
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
Reference 2
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T18:54:01.267418Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 69825b9b-10e1-41a3-a31a-afc7b65cc0fb · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
Reference 29
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:19:54.045629Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 61b24ae2-7ad7-412c-9923-1513095c6c94 · inbound
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement cites this paper.
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
Reference 2
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T10:49:56.166582Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.