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REVIEW 4 major objections 5 minor 52 references

AGON: Automated Design Framework for Customizing Processors from ISA Documents

T0 review · 4 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read AGON turns ISA documents into customized out-of-order processors that beat an expert-designed CPU by an average of 2.35×.

desk verdict A genuine framework contribution with a real IR idea, but the headline 2.35x/79.5% comparison is undermined by an uncalibrated simulator and a mismatch between what is simulated and what is synthesized. read the letter →

arxiv 2412.20954 v2 pith:5M4LBC75 submitted 2024-12-30 cs.AR

Chongxiao Li , Di Huang , Pengwei Jin , Tianyun Ma , Husheng Han , Shuyao Cheng , Yifan Hao , Yongwei Zhao
show 7 more authors
Guanglin Xu Zidong Du Rui Zhang Xiaqing Li Yuanbo Wen Xing Hu Qi Guo
This is my paper · ORCID
classification cs.AR
keywords processordesignautomationLLM-basedhardwaregenerationintermediaterepresentationnOPfunctionout-of-orderRISC-VcustomizationspaceexplorationPPAoptimization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

AGON is a framework for automatically turning natural-language instruction-set architecture (ISA) documents into working out-of-order (OoO) processor designs. The paper claims that, using an intermediate representation built from nano-operator functions (nOP functions), an LLM can generate instruction functionality accurately enough that a human only fixes a few lines of code per processor. AGON then schedules and optimizes the nOP operations into hardware, and its auto-tuning searches over microarchitecture configurations. The claimed result is that the resulting customized processors beat BOOM, an expert-designed general-purpose RISC-V CPU, by an average of 2.35× in performance while using about 79.5% of its area. This matters because it points toward a practical path from specifications to high-performance processors without months of manual RTL design.

What carries the argument

The load-bearing mechanism is the nano-operator function (nOP function) intermediate representation: a small fixed vocabulary of storage, program-counter, and arithmetic-logic operations combined as a dataflow graph. It makes instruction semantics expressible in a few lines of Python-like code, executable immediately for verification, and independent of how the hardware executes them. That decoupling is what lets AGON apply rule-based functional-equivalence transformations, fuse nOPs into functional units via instruction.fuse and isa.auto_fuse, and explore over 179 million microarchitecture configurations with processor.auto_config without touching the functional description. The same nOP graph is compiled into a cycle-accurate simulator and, for a subset of fusion strategies, synthesized into Chisel-based RTL that plugs into the BOOM core.

What would settle it

Run the same eight benchmarks on BOOM's RTL (or an FPGA prototype) at the small, large, and giga configurations and compare the measured cycle counts with the cycle counts AGON's simulator reports; if the real BOOM cycles are substantially lower than simulated, the claimed 2.35× speedup would shrink or disappear.

Watch

Extended reading notes

Core claim

The paper's central claim is that the bottleneck in LLM-based processor design is not the LLM itself but the representation it is asked to produce. AGON defines a nano-operator function (nOP function) intermediate representation: each instruction is written as a Python-like dataflow of small operations such as register reads, shifts, XORs, and PC updates. Because nOP functions are executable and hide port connections, sequential structures, and bit-width management, LLMs can generate them accurately, with a pass@1 of 95.9% over the 49 RV64I instructions and high success on most tested crypto and packed-SIMD extensions. AGON compiles these functions into a cycle-accurate out-of-order processor simulator, applies rule-based fusion and microarchitecture search, and synthesizes the result into RTL in the style of the BOOM core. Across eight domain-specific benchmarks and three BOOM configurations, the customized AGON processors are faster in 23 of 24 scenarios, with an average 2.35× speedup and an average area of 79.5% of BOOM's.

Load-bearing premise

The load-bearing premise is that AGON's simulator reports BOOM's performance truthfully, because the paper measures the baseline with that simulator instead of running BOOM's actual RTL or physical hardware.

Editorial extensions

If this is right

  • A new instruction-set extension described in natural language can be prototyped as an out-of-order processor with only a handful of human-fixed lines; the paper reports average debug effort of 2 to 9.67 lines across its eight benchmark processors.
  • LLM-based generation becomes practical at processor scale: with the nOP representation, the LLM succeeded on 95.9% of RV64I instructions and on 18 of the more complex crypto and packed-SIMD instructions without human fixes.
  • PPA-aware auto-tuning produces a genuine design-space frontier: changing the fusion gain threshold shifts designs between high-performance/larger-area and lower-performance/smaller-area regions.
  • In area-constrained comparisons, AGON's customized processors beat the expert-written BOOM in 23 of 24 tested scenarios, including a 17.40× speedup on the matrix-multiplication benchmark under the small-BOOM area budget.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The functionality/optimization decoupling could extend beyond CPUs: if the nOP vocabulary were broadened, the same pipeline could generate accelerators or vector units, which share the HDL difficulties that trip up LLMs.
  • The current auto-tuning objective is cycle count times area; optimizing for energy or peak power would likely produce different Pareto fronts and could be evaluated with the same simulator and estimator.
  • Because nOP functions are executable and rule-based, they could support formal equivalence checking against later hand-written RTL, strengthening the correctness claim beyond simulation-based verification.
  • The 2.35× figure is tied to simulator fidelity; if the simulator were calibrated against BOOM RTL simulation or FPGA prototyping, the comparison would test how the advantage carries to real hardware.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. AGON is a framework that takes RISC-V ISA extension documents and, with the help of an LLM and a custom intermediate representation called nOP functions, generates out-of-order processor RTL with minimal human intervention. The paper's contributions are an executable nOP-function IR, multi-level verification primitives (instruction, ISA, processor), scheduling/fusion primitives, a Bayesian DSE auto-configuration primitive, and an LLM-based few-shot generation flow with self-debugging and clustering. The headline experimental claim, in Section VII-C, is that AGON-designed customized processors are on average 2.35x faster than BOOM across 24 scenarios while using only 79.5% of BOOM's area. The paper also reports high LLM pass rates for nOP-function generation relative to direct Chisel generation, and lower reported human debugging effort than prior LLM-based CPU generation works.

Significance. If the performance and area claims are substantiated, AGON would be a meaningful step toward practical LLM-assisted processor customization: the nOP IR is a plausible mechanism for turning ISA documents into executable functional descriptions, the multi-level verification approach is sensible, and the reported pass@1 numbers (e.g., 95.9% for RV64I, and 18 extended instructions generated without human intervention) are concrete evidence that the IR improves LLM reliability over direct HDL generation. The comparison to BOOM is an ambitious and useful target for an automated flow. However, the central quantitative claim currently rests on an unvalidated internal simulator and on a synthesis path that implements only a subset of the simulated optimizations, which prevents the reader from attributing the reported speedup and area to the same generated design. These issues are fixable but require additional experiments or a significant recasting of the claims.

major comments (4)
  1. [§V-E, §VII-C] The headline comparison is internally inconsistent about what design is being measured. Section V-E states that synthesis 'temporarily only support[s] fusing all AL-related nOPs within each instruction' and that 'instructions with three or more inputs' are deferred to future work, yet Section VII-C uses isa.auto_fuse(gain_th=0) and processor.auto_config to produce the cycle counts in Figure 8, and auto_fuse(gain_th=0) is explicitly described in Section VII-C as fusing all nOPs into one OP. The simulated design can therefore include cross-instruction fusion patterns and instructions with three or more inputs, none of which the current synthesize() primitive can turn into RTL. The area reported in Figure 8, by contrast, comes from synthesized RTL per Section VII-A. Consequently, the 2.35x speedup and 79.5% area cannot both be attributed to the same processor as generated by the current framework. The authors should either implement the full fusion and multi-input instruction support in RTL, or report performance for the synthesized subset, and clearly label the two designs separately.
  2. [§VII-A] The BOOM baseline is not independently measured. The paper states, 'Applying BOOM configurations, we use our simulator to report the performance of benchmark applications compiled to RV64I running on BOOM as the baseline.' Both the AGON cycle counts and the BOOM cycle counts therefore come from the same AGON cycle-accurate simulator, with no calibration against BOOM RTL simulation, FPGA prototyping, or silicon. If the simulator is optimistic for AGON's microarchitecture or pessimistic for BOOM's, the 2.35x figure becomes an artifact of the model. The authors should validate the simulator against actual BOOM RTL simulation on the RV64I baseline, and report the resulting error bars or correction factors before using it to support the central performance claim.
  3. [§VII-C, §VII-A] The area comparison mixes two different measurement methodologies. For AGON processors, Section VII-A says the generated circuit is synthesized with a commercial 65nm flow to obtain 'accurate area.' For BOOM, Section VII-C says the area limit is 'the area of BOOM estimated by McPAT.' McPAT estimates of BOOM's area are not the same as a synthesis result (McPAT uses analytical models and requires calibration), so the reported 79.5% area ratio is not a like-for-like comparison. The authors should synthesize BOOM with the same 65nm flow, or at least validate the McPAT estimate against a synthesis of BOOM, before reporting the area ratio as a headline result.
  4. [§VII-C] The performance comparison conflates ISA-extension gains with microarchitectural optimization. The AGON processors execute the domain-specific extended instructions (for example, SHA256/SHA512 and the packed-SIMD instructions in Table V), while the BOOM baseline is reported with the same benchmarks 'compiled to RV64I.' A large part of the speedup is then attributable to the added custom instructions themselves, not to the auto_fuse/auto_config tuning primitives that Section VII-C is intended to demonstrate. To isolate the contribution of AGON's optimization primitives, the authors should also report an AGON processor that runs the same benchmark compiled to RV64I only, or otherwise control for the ISA difference, so that the reader can see how much of the 2.35x comes from the microarchitecture flow rather than from the instruction set extensions.
minor comments (5)
  1. [§VI, Table VI] The pass@1 rates are reported for only three trials per instruction, and several instructions (sha512sig1, kslra32, clz32, kwmmul) show 0% pass@1. The text says AGON 'succeeds in generating 18 instructions without human intervention' but it is not clear exactly which instructions are counted and how the 0% cases interact with the debugging LoC in Table VII. Please clarify the definition of 'without human intervention' and report the number of trials or confidence intervals.
  2. [Abstract, §V-D] The abstract and Section V-D use the phrase 'correctness guarantees,' but the described verification is test-based (test IOs and test programs), not a formal proof. Suggest softening 'guarantees' to something like 'multi-level verification' to match what is actually implemented.
  3. [Figure 7] The Pareto-front markers ('darker dots') are difficult to distinguish in the grayscale printing, and the figure does not indicate the number of simulated design points per benchmark. Please add a legend and report the size of the explored design space for each benchmark.
  4. [§VII-A] The experimental setup does not state the compiler used to generate the benchmark binaries, nor whether the same compiler and optimization flags were used for the BOOM RV64I baseline and the AGON extended-ISA binaries. Please specify the toolchain and flags, since this can materially affect cycle counts.
  5. [§V-C] The DSE cost function in Equation 4 uses area(x) from the simulator (McPAT), while the final reported area comes from synthesis. The paper should state explicitly that the optimization target and the reported metric are produced by different estimation methods, and discuss the resulting discrepancy.

Circularity Check

1 steps flagged · score 6.0 of 10

The reported 2.35x speedup is an in-sample result: configurations are auto-tuned on the same benchmarks and the same AGON simulator that later report both AGON and BOOM cycle counts, and the simulated fusion features used for performance are not all supported by the synthesized RTL used for area.

  1. fitted input called prediction [Section VII-C, 'AGON Enables Optimization' (setup in Section VII-A)]
    "we take the area of BOOM estimated by McPAT as the limitation, utilizing isa.auto_fuse(gain_th=0) and processor.auto_config primitives to optimize the performance of ASIPs with a smaller area than BOOM. Applying BOOM configurations, we use our simulator to report the performance of benchmark applications compiled to RV64I running on BOOM as the baseline."

    The cycle counts reported for AGON in Figure 8 are the values minimized by processor.auto_config (Equation 2: x* = argmin f(cycle(x), area(x), power(x))) using the same embedded simulator and the same eight benchmark programs. The resulting 'surpasses BOOM in 23 out of 24 scenarios' claim therefore restates the optimizer's selection criterion rather than testing an independent prediction on a fixed design. The BOOM baseline is not similarly auto-tuned, and both sides are scored by the proposer's uncalibrated simulator, so the headline 2.35x speedup is an in-sample evaluation of the objective function, not an externally grounded comparison.

full rationale

AGON's core technical contributions are not definitionally circular: the nOP IR, the LLM generation flow, and the synthesis-to-Chisel path are self-contained mechanisms with assessable outputs. No load-bearing chain depends on the authors' prior work; reference [18] is background citation, not the argument. The central circularity concern is the evaluation loop: processor.auto_config optimizes cycle counts from AGON's simulator on the same benchmark programs that then produce the headline 2.35x comparison, with the BOOM baseline also scored by that same simulator. That makes the central claim in-sample and self-referential to the proposed tool. A separate limitation in Section V-E compounds this: only AL-related nOP fusion within each instruction is supported at synthesis time, while 'instructions with three or more inputs' and 'other fusing strategies' run only in the simulator, so the simulated performance and the synthesized area in Figure 8 may describe different designs. This is an internal-validity problem rather than an additional fitted-parameter circularity, and it justifies a partial-circularity score rather than a clean bill of health.

Assumptions & free parameters 4 free parameters · 6 assumptions · 2 invented entities

The design rests on the fidelity of AGON's own simulator, on the completeness of the nOP abstraction, and on unverified rule-based transformations. The nOP IR is introduced by this paper and has no independent evidence outside the flow. The performance and correctness claims are therefore contingent on these internal assumptions.

free parameters (4)
  • auto_fuse gain threshold = 0.5 for balanced Pareto; 0.0 for full fusion
    The paper compares auto_fuse with gain thresholds 0, 0.5, and none. The threshold is a user-chosen knob that shapes the explored design space and the final optimized design.
  • DSE design space and search budget = not stated
    processor.auto_config runs parallelized Bayesian optimization over a 179 million point space (Table IV), but the iteration count and acquisition parameters are not reported, so the reported optimum depends on an unspecified search budget.
  • target frequency for nOP synthesis = 2 GHz
    Used to estimate nOP arrival times and slack (Table III), which grounds the fusion cycle-delay estimates in Equation 1.
  • LLM generation parameters = temperature 0.3, up to 3 syntax-check rounds, up to 9 samples
    These settings affect pass@1 and the clustering-based selection, so the reported generation accuracy is conditional on them.
assumptions (6)
  • domain assumption The AGON cycle-accurate simulator faithfully models both the AGON OoO processor and BOOM microarchitectures without calibration.
    Section VII-A and VII-C use the simulator to report both AGON and BOOM cycle counts. No validation against BOOM RTL, FPGA, or published BOOM measurements is provided.
  • domain assumption The nOP categories (storage, PC, AL) cover all instruction functionality for von Neumann architectures.
    Section IV claims the three nOP types 'cover the overall functional space of instructions'.
  • domain assumption Rule-based transformations in AGON preserve instruction functionality.
    Section V claims the compiler and transformations 'guarantee process correctness', but no formal equivalence proof is given.
  • domain assumption GPT-4 can generalize from 3 MIPS few-shot examples to generate RISC-V nOP functions.
    Section VI uses 3-shot MIPS examples; generalization to RISC-V and P/Zknh extensions is empirically evaluated but not guaranteed.
  • domain assumption McPAT and 65nm synthesis provide accurate area and power estimates.
    Section V-C and VII-A rely on McPAT for area and power and a commercial EDA tool for synthesis; no silicon measurement is reported.
  • domain assumption The benchmark set is representative of domain-specific custom-processor workloads.
    Seven of eight benchmarks come from Nuclei-Software P-extension code; results may not generalize to other domains.
invented entities (2)
  • nOP function IR
    purpose: Intermediate representation that describes instruction functionality as compositions of nano-operators, decoupling functionality from microarchitectural optimization.
    The IR is evaluated only within AGON's own flow. No external implementation or benchmark uses nOP functions outside this paper, so there is no independent falsifiable handle.
  • nOP-level dynamic scheduling in the OoO processor
    purpose: The processor schedules individual nOPs rather than whole instructions as the dynamic unit, enabling better functional-unit reuse.
    Only simulated within AGON's simulator. The synthesized BOOM integration does not implement nOP-level scheduling (it fuses nOPs per instruction and defers other strategies, Section V-E), so there is no independent evidence.

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Cite this review

Pith. "Pith review of AGON: Automated Design Framework for Customizing Processors from ISA Documents." pith.science (2026). https://pith.science/paper/5M4LBC75

@misc{pith2026241220954,
  author       = {Pith},
  title        = {Pith review of: AGON: Automated Design Framework for Customizing Processors from ISA Documents},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5M4LBC75}},
  note         = {Machine review of arXiv:2412.20954}
}
abstract

Customized processors are attractive solutions for vast domain-specific applications due to their high energy efficiency. However, designing a processor in traditional flows is time-consuming and expensive. To address this, researchers have explored methods including the use of agile development tools like Chisel or SpinalHDL, high-level synthesis (HLS) from programming languages like C or SystemC, and more recently, leveraging large language models (LLMs) to generate hardware description language (HDL) code from natural language descriptions. However, each method has limitations in terms of expressiveness, correctness, and performance, leading to a persistent contradiction between the level of automation and the effectiveness of the design. Overall, how to automatically design highly efficient and practical processors with minimal human effort remains a challenge. In this paper, we propose AGON, a novel framework designed to leverage LLMs for the efficient design of out-of-order (OoO) customized processors with minimal human effort. Central to AGON is the nano-operator function (nOP function) based Intermediate Representation (IR), which bridges high-level descriptions and hardware implementations while decoupling functionality from performance optimization, thereby providing an automatic design framework that is expressive and efficient, has correctness guarantees, and enables PPA (Power, Performance, and Area) optimization. Experimental results show that superior to previous LLM-assisted automatic design flows, AGON facilitates designing a series of customized OoO processors that achieve on average 2.35 $\times$ speedup compared with BOOM, a general-purpose CPU designed by experts, with minimal design effort.

Figures

Figures reproduced from arXiv: 2412.20954 by the authors.

Figure 1
Figure 1. Comparing AGON with existing synthesis work in terms of needed [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. The overview of AGON. (a) AGON decouples optimization from functionality, using nOP functions to describe the processor functionality, and [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Concepts and examples about nOPs, nOP functions and nOP dataflow [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: Fusing nOPs with instruction.fuse primitive. (a) The original nOP dataflow graph of instruction sha512sum0. The minimum instruction execution cycle delay is 4 cycles. (b) After fusing with two patterns ror and xor3, the delay is reduced to 2 cycles. B. ISA-level Primit…
Figure 5
Figure 5. Figure 5: The AGON’s nOP function generation method. After the nOP [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Illustration of nOP specifications and few-shot examples. nOP [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 8
Figure 8. Figure 8: The cycles and area of customized processors designed with AGON [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 7
Figure 7. Figure 7: The results of the auto-tuning for our 8 benchmark applications. [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.