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Scaling and assigning resources on ion trap QCCD architectures

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arxiv 2408.00225 v1 pith:FYWYLZYU submitted 2024-08-01 quant-ph cs.ET

classification quant-phcs.ET
keywords quantumtrapqccdqubitsarchitecturescandidatesfidelitynovel
verification ladder T0 review T1 audit T2 compute T3 formal
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Ion trap technologies have earned significant attention as potential candidates for quantum information processing due to their long decoherence times and precise manipulation of individual qubits, distinguishing them from other candidates in the field of quantum technologies. However, scalability remains a challenge, as introducing additional qubits into a trap increases noise and heating effects, consequently decreasing operational fidelity. Trapped-ion Quantum Charge-Coupled Device (QCCD) architectures have addressed this limitation by interconnecting multiple traps and employing ion shuttling mechanisms to transfer ions among traps. This new architectural design requires the development of novel compilation techniques for quantum algorithms, which efficiently allocate and route qubits, and schedule operations. The aim of a compiler is to minimize ion movements and, therefore, reduce the execution time of the circuit to achieve a higher fidelity. In this paper, we propose a novel approach for initial qubit placement, demonstrating enhancements of up to 50\% compared to prior methods. Furthermore, we conduct a scalability analysis on two distinct QCCD topologies: a 1D-linear array and a ring structure. Additionally, we evaluate the impact of the excess capacity -- i.e. the number of free spaces within a trap -- on the algorithm performance.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Moveless: Minimizing Overhead on QCCDs via Versatile Execution and Low Excess Shuttling

    quant-ph 2025-08 conditional novelty 7.0 of 10

    Moveless compiles stabilizer-code syndrome extraction for QCCD trapped ions with ancilla-only shuttling, dynamic stabilizer reordering, and ancilla reuse, achieving up to 5.24x lower latency and up to two orders of ma...

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