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Differentiable Weightless Neural Networks

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arxiv 2410.11112 v5 pith:ZQRNQIG3 submitted 2024-10-14 cs.LG cs.AI

Differentiable Weightless Neural Networks

Alan T. L. Bacellar , Zachary Susskind , Mauricio Breternitz Jr. , Eugene John , Lizy K. John , Priscila M. V. Lima , Felipe M. G. Fran\c{c}a This is my paper
classification cs.LG cs.AI
keywords dwnsaccuracyneuraltheyareadifferentiableefficiencyhardware
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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We introduce the Differentiable Weightless Neural Network (DWN), a model based on interconnected lookup tables. Training of DWNs is enabled by a novel Extended Finite Difference technique for approximate differentiation of binary values. We propose Learnable Mapping, Learnable Reduction, and Spectral Regularization to further improve the accuracy and efficiency of these models. We evaluate DWNs in three edge computing contexts: (1) an FPGA-based hardware accelerator, where they demonstrate superior latency, throughput, energy efficiency, and model area compared to state-of-the-art solutions, (2) a low-power microcontroller, where they achieve preferable accuracy to XGBoost while subject to stringent memory constraints, and (3) ultra-low-cost chips, where they consistently outperform small models in both accuracy and projected hardware area. DWNs also compare favorably against leading approaches for tabular datasets, with higher average rank. Overall, our work positions DWNs as a pioneering solution for edge-compatible high-throughput neural networks.

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Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. KANEL\'E: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation

    cs.AR 2025-12 conditional novelty 7.0

    Quantized, pruned Kolmogorov-Arnold Networks can be compiled directly into FPGA lookup tables, achieving extreme latency/resource reductions and matching state-of-the-art LUT-based networks on several benchmarks.

  2. Fully Trainable Deep Differentiable Logic Gate Networks and Lookup Table Networks

    cs.LG 2026-07 conditional novelty 6.5

    Training connections as well as gate/LUT functions lets deep logic-gate and lookup-table networks match fixed-wiring accuracy with far fewer gates (e.g. 8k vs ~384k on MNIST).

  3. FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs

    cs.AR 2026-07 conditional novelty 6.0

    A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.

  4. Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications

    cs.NE 2025-11 unverdicted novelty 4.0

    Post-training quantization reduces U-Net memory by 4x with maintained or improved segmentation accuracy, and a genetic-algorithm approach trains LUT-based binary networks for 10-15 ns FPGA inference without DSP or BRAM.