Paper Citation Record · LEDGER

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design

As of 15 August 2026, this Paper Citation Record lists 19 of 19 outbound references and 1 inbound Pith citation observation for arXiv:2411.08510.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2411.08510 v1

Coverage vector

measured 19 of 19 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-12T21:36:11.973662Z

measured 20 of 20 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-09T22:24:49.983944Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-09T22:24:50.084305Z

Reference resolution

19 of 19 outbound references displayed

verified exact0
verified fuzzy14
unresolved5
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation bdff847b-a45b-4853-bfc9-71e0bfd8c30e · outbound

This paper cites Coverage-Directed Test Generation Auto- mated by Machine Learning – A Review,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Coverage-Directed Test Generation Auto- mated by Machine Learning – A Review,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.329537Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d6e557f3-332a-4553-819d-439e1d93e713 · outbound

This paper cites Improving Coverage of Simulation- Based Verification by Dedicated Stimuli Generation,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Improving Coverage of Simulation- Based Verification by Dedicated Stimuli Generation,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.315150Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0a3b81a9-3d96-467c-bf6d-783e674c30aa · outbound

This paper cites A VERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design A VERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.300997Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0a8c2a9b-129c-433d-8cf3-97752096b7ba · outbound

This paper cites Stimulus Generation for Con- strained Random Simulation,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Stimulus Generation for Con- strained Random Simulation,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.286506Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 034a59f1-6c7c-454f-b52b-3e138e6b2099 · outbound

This paper cites Chip-Chat: Challenges and Opportunities in Conversational Hardware Design,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Chip-Chat: Challenges and Opportunities in Conversational Hardware Design,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.271509Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a81f2c35-f915-432c-bb94-f480c81a52bc · outbound

This paper cites Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.256097Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e7d04060-35ae-43b8-9332-882777e1f142 · outbound

This paper cites Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.240808Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0760d29b-d852-4945-8624-8f72a27706d1 · outbound

This paper cites ChipGPT: How Far Are We From Natural Language Hardware Design,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design ChipGPT: How Far Are We From Natural Language Hardware Design,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-12T21:36:11.921229Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0caa5c51-2096-4510-be46-73e0e4acc77e · outbound

This paper cites VerilogEval: Evaluating large language models for verilog code generation,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design VerilogEval: Evaluating large language models for verilog code generation,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.225935Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 8d74b5fb-688e-4348-a63a-90d29f9cd7cb · outbound

This paper cites Machine Learning in Advanced IC Design: A Methodological Survey,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Machine Learning in Advanced IC Design: A Methodological Survey,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.209582Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fe1cf70c-7b53-4e3c-aaed-bf40d52164ef · outbound

This paper cites Classification-Based Automatic HDL Code Generation Using LLMs,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Classification-Based Automatic HDL Code Generation Using LLMs,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.192924Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 4020c6c7-4f9f-45dc-a861-2739a2037f58 · outbound

This paper cites RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-12T21:36:11.939463Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6bdf6cb3-5d5b-456c-9fbe-bdd5b4049b08 · outbound

This paper cites AutoChip: Automating HDL Generation Using LLM Feedback.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design AutoChip: Automating HDL Generation Using LLM Feedback

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-12T21:36:11.944732Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 724a5186-1588-48ae-beb1-61a516e050b9 · outbound

This paper cites LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-12T21:36:11.949534Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a11680a2-bb48-4a86-847f-12e111d28346 · outbound

This paper cites Au- toBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Au- toBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.177876Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cc5d1c6d-68be-412a-9ba1-fbb1b94b1e9b · outbound

This paper cites A Survey on Hallucination in Large Language Models: Principles, Taxonomy, Challenges, and Open Questions.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design A Survey on Hallucination in Large Language Models: Principles, Taxonomy, Challenges, and Open Questions

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-12T21:36:11.959111Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3b6a32d2-918c-4559-a3c0-22fed537e037 · outbound

This paper cites Large Language Models Can be Lazy Learners: Analyze Shortcuts in In-Context Learning,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Large Language Models Can be Lazy Learners: Analyze Shortcuts in In-Context Learning,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.163039Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5636d7f5-e868-4929-9c60-acc2461bd661 · outbound

This paper cites The ICARUS verilog compilation system,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design The ICARUS verilog compilation system,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.147355Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e9e0d649-9bf2-4105-91ac-78ae80eca4ec · outbound

This paper cites Problem sets - HDLBits,.

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design Problem sets - HDLBits,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-12T21:36:12.130690Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Pith citing papers

Observation 9247417b-9c9c-409a-b4b0-d6c9712e8399 · inbound

SoK: Towards Effective Automated Vulnerability Repair cites this paper.

SoK: Towards Effective Automated Vulnerability Repair CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design

Reference 216

Resolution: verified exact; local_arxiv, observed 2026-08-09T22:24:50.092214Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.