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A Universal Circuit Set Using the $S_3$ Quantum Double
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abstract
One potential route toward fault-tolerant universal quantum computation is to use non-Abelian topological codes. In this work, we investigate how to achieve this goal with the quantum double model $\mathcal{D}(S_3)$ -- a specific non-Abelian topological code. By embedding each on-site Hilbert space into a qubit-qutrit pair, we give an explicit construction of the circuits for creating, moving, and locally measuring all non-trivial anyons. We also design a specialized anyon interferometer to remotely measure the total charge of well-separated anyons; this avoids fusion, which would compromise fault tolerance. These protocols enable the implementation of a universal gate set proposed by Cui et al. and active quantum error correction of the circuit-level noise during the computation process. To further reduce the error rate and facilitate error correction, we encode each physical degree of freedom of $\mathcal{D}(S_3)$ into a novel, quantum, error-correcting code, enabling fault-tolerant realization, at the logical level, of all gates in the anyon manipulation circuits. Our proposal offers a promising path to realize robust universal topological quantum computation in the NISQ era.
Forward citations
Cited by 3 Pith papers
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Self-dual $S_3$ gauge theory in 2+1d: lattice model and topological phase transitions
A new sign-problem-free lattice Hamiltonian realizes the S3 quantum double with electric-magnetic duality as translation, yielding a tetracritical Ising boundary and three predicted topological transitions.
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Tensor Network Representations for Intrinsically Mixed-State Topological Orders
A Choi-state anyon condensation protocol builds fixed-point tensor networks for intrinsic mixed-state topological orders from decohered pure states.
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Non-Clifford gates between stabilizer codes via non-Abelian topological order
A protocol uses the non-Abelian S3 quantum double as an intermediate to implement a controlled charge-conjugation (CC) gate between qubit and qutrit surface codes.
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