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SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read An LLVM-based pass automatically detects parallel low-precision arithmetic in HLS designs and packs the operations into single FPGA DSPs, cutting average DSP usage by 70% for additions and 50% for multiplications and multiply-and-adds…

desk verdict An LLVM-based HLS pass for automatic DSP packing that is new and mostly well-validated; the main gap is the missing functional-equivalence check on the custom RTL replacement. read the letter →

arxiv 2411.11384 v1 pith:BYJZH263 submitted 2024-11-18 cs.AR

Giovanni Brignone , Roberto Bosio , Fabrizio Ottati , Claudio Sansoè , Luciano Lavagno This is my paper · ORCID
classification cs.AR
keywords High-levelsynthesisFPGADSPpackingSuperword-levelparallelismLLVMSIMDMultiply-and-addElectronicdesignautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

SILVIA is an open-source LLVM transformation pass that slots into a high-level synthesis (HLS) flow between the frontend and the backend and automatically finds operations that can share one FPGA DSP. It packs four 12-bit (or two 24-bit) additions or subtractions, two 8-bit multiplications or multiply-and-adds with a shared operand, and four 4-bit multiplications with a common operand, all without manual edits to the C++ design. The paper's central claim is that this makes DSP efficiency a compiler responsibility instead of a designer's hand-tuning task. On a diverse set of accelerators, the pass reduced DSP utilization by 70% on average for additions and 50% for multiplications and multiply-and-adds, left throughput unchanged, and matched the quality of manually optimized convolutional neural network accelerators.

What carries the argument

The load-bearing mechanism is the SILVIA pass skeleton: a per-basic-block 'candidate, tuple, pack' pipeline implemented as an LLVM transformation pass, with two concrete specializations. The base class collects candidate instructions (or addition-tree patterns), moves uses as late as possible to create insertion room, groups candidates into valid tuples, and replaces each tuple with a packed-operation call; virtual functions let each specialization define which candidates are legal and how the tuple is packed. The two provided specializations are SILVIAAdd, which targets the DSP SIMD modes (four 12-bit or two 24-bit adds/subtracts), and SILVIAMuladd, which targets factor-2 packed multiply-and-adds with shared operands and factor-4 packed 4-bit multiplications, including a packing for four unsigned 4-bit factors times one common signed or unsigned factor. The packed function is either described in the IR or left as a placeholder module that is later swapped for a custom RTL implementation.

What would settle it

Synthesize any SILVIA-optimized design with the placeholder modules replaced, then run an exhaustive or randomized bit-accurate simulation of the packed RTL against the original scalar operations for all supported input widths; a single mismatch in the four-12-bit adder, the two-24-bit adder, the factor-2 MAD, or the factor-4 multiplier would invalidate the reported DSP savings. A second check is to build the dependence pattern of Fig. 5 and measure whether the initiation interval grows from 2 to 3 cycles as predicted when packing creates a new critical cycle.

Watch

Extended reading notes

Core claim

The paper establishes that superword-level parallelism naturally present in HLS designs, often exposed by loop unrolling, can be recognized and exploited at the LLVM intermediate-representation level without source-code changes. The key move is to treat a basic block as a set of candidate arithmetic instructions, rearrange their uses as late as possible (ALAP) so that packed replacement calls have a valid insertion point, group independent candidates into tuples that satisfy the DSP packing constraints, and replace each tuple with a call to a packed-operation function that the HLS backend binds to a single DSP. This yields a 70% average reduction in DSPs for additions and a 50% average reduction for multiplications and multiply-and-adds across the benchmarks, with no change to pipeline initiation intervals; in CNN case studies the automatically optimized designs occupy the same DSP-versus-throughput points as manually tuned ones.

Load-bearing premise

The central claim collapses if the custom RTL modules that replace SILVIA's placeholder functions do not compute bit-identically to the original scalar additions, multiplications, and multiply-and-adds for every supported width and signedness.

Editorial extensions

If this is right

  • HLS code can stay scalar and portable: the pass finds the packing opportunities after frontend optimization, so designers no longer hand-insert bit manipulation or RTL modules to use DSP SIMD modes.
  • Across the measured benchmarks, average DSP utilization drops by 70% for additions and 50% for multiplications and multiply-and-adds, while initiation intervals, and therefore throughput, are unchanged.
  • In the CNN case studies, SILVIA-optimized designs match manually optimized accelerators in the DSP-versus-throughput trade-off, reaching roughly double throughput when the DSP count is capped.
  • The base pass is extensible: adding a new packed operation requires only candidate detection and tuple-packing routines, with the ALAP scheduling, tuple-validity checks, and dead-code cleanup reused.
  • The cost side is explicit: packed pipelines are about 27% deeper on average, using more flip-flops and memory LUTs, while DSP savings still reduce average power by roughly 8-10%.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If SILVIA's reliability holds on larger designs, the natural next step is to let the HLS scheduler feed latency information back into tuple formation, eliminating the edge case where packing creates a new critical cycle and increases the initiation interval.
  • The same candidate-tuple-pack skeleton could be retargeted to other DSP families or to mixed-precision operations by re-deriving the shared-operand and overflow constraints for those architectures.
  • The resource-sharing extension mentioned in the paper, which would pack even single addition instructions so they share a functional unit with packed tuples, could reduce DSP counts further on designs with many unpaired operations.
  • Because packing is done at the IR level after frontend width minimization, the approach could combine with other IR-level transformations, such as loop tiling or operation fusion, to expose more packable parallelism than unrolling alone.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents SILVIA, an open-source LLVM transformation pass that runs between the frontend and backend of AMD Vitis HLS and automatically identifies superword-level parallelism in HLS designs, packing multiple additions, multiplications, and multiply-and-adds into single DSP slices. The pass is specialized into SILVIAAdd, for four 12-bit or two 24-bit SIMD additions/subtractions, and SILVIAMuladd, for two 8-bit MADs or four 4-bit multiplications with a shared operand. The evaluation covers addition-intensive and multiplication-intensive benchmarks plus CNN accelerators built with NN2FPGA and FINN, reporting average DSP reductions of 70% for additions and 50% for multiplications/MADs relative to a DSP-bound baseline, with equal or improved throughput and comparable quality of results to manually optimized CNN designs.

Significance. If the reported results are correct, SILVIA is a useful contribution: it automates a low-level DSP-packing optimization that currently requires manual RTL or source-level intervention, integrates with a commercial HLS flow, and is released as open source. The CNN case study is a particular strength, because it directly compares the automated flow against two established manually optimized frameworks and shows matching DSP-versus-throughput design points. The work also demonstrates that the LLVM IR level is a practical place to apply DSP packing in HLS. The main limitation is that the correctness of the transformed hardware is not experimentally established: the ALAP use-motion and the custom RTL replacement modules are both asserted to be semantics-preserving, but no simulation, co-simulation, or hardware output comparison is reported. The resource savings therefore cannot yet be fully separated from the possibility that the optimized designs compute something different from the original source.

major comments (3)
  1. [§3.2.1, Fig. 4] The ALAP use-motion moves uses of candidate values later within the basic block; in the Fig. 4 example this moves a store of c0 across a load of a1, i.e., it is a memory reordering. The paper states that dependencies are preserved via def-use chains and LLVM alias analysis, and that function calls are conservatively treated as aliasing, but it does not prove that the motion is semantics-preserving for all moved memory operations, and it does not report any check that no store was moved across an aliasing load in the evaluated benchmarks. A single unsound reordering would change accelerator behavior while preserving all reported resource counts. The authors should add a correctness validation of the transformed IR, for example by comparing simulation outputs before and after the pass on every benchmark, or by formally verifying that the pass only moves a memory operation across another operation when aliasing is disproved.
  2. [§3.4, §2.3] The custom DSP-packed RTL modules that replace the HLS-generated placeholder functions are not described and are never shown to be functionally equivalent to the original scalar operations. This is load-bearing: if the replacement modules are not bit-accurate for the four-12-bit SIMD adder, the two-24-bit adder, the factor-2 MAD packing, or the factor-4 unsigned multiplication packing with its correction logic, all DSP savings in Tables 1 and 2 would be measured on incorrect hardware even if the LLVM transformation is correct. The paper should provide the module implementations or at least a detailed RTL description, together with a testbench or co-simulation that compares the packed outputs against the original C++/LLVM semantics on the actual benchmark data.
  3. [§4, Tables 1 and 2] The general-purpose benchmark results report only post-implementation resource, timing, and power numbers, with no experiment that verifies the computed outputs of the SILVIA-optimized designs against the baseline designs. The CNN case study states that throughput is measured from hardware execution, but it does not state that the hardware outputs were compared with expected values. Given that the two transformation steps above carry the correctness burden, the absence of any end-to-end functional check leaves the central claim that SILVIA preserves functionality unsupported. A simple addition would be to run a hardware or RTL simulation for each benchmark and compare the outputs of the baseline and SILVIA versions.
minor comments (5)
  1. [§1 vs. Abstract/§4/§5] The Introduction reports average savings of 60% for additions and 45% for multiplications/MADs, while the Abstract, Section 4, and the Conclusion report 70% and 50%. The measured geometric means in Table 1 (0.30 and 0.50 normalized DSP utilization) support the 70%/50% figures; the Introduction numbers should be corrected.
  2. [§4, Table 1] All resource and power numbers come from a single synthesis/implementation run, and the paper does not report run-to-run variation or sensitivity to synthesis settings. For differences such as the 9% average LUT overhead or the Fmax variations, a few repeated runs or at least a statement about determinism of the toolchain would help the reader judge significance.
  3. [§2.3, Fig. 3] The notation E[3:1]3 in Equation (4) is confusing; it should be written as E3[3:1] to denote the three most significant bits of operand E3. This would make the bit mapping in Fig. 3a easier to follow.
  4. [§3.3 and §3.4] The distinction between placeholder functions that are directly implemented in LLVM IR and those replaced by custom RTL modules is not entirely clear: Section 3.3 says HLS generates a dedicated module for a placeholder, and Section 3.4 says SILVIA re-implements the Vitis black-box functionality. A concrete example showing the LLVM IR and the corresponding placeholder/RTL interface for one packed operation would clarify the mechanism.
  5. [§3.5.1] The discussion of the new critical cycle introduced by packing is clear, but the claim that this scenario was never encountered in the benchmarks is stated without supporting data. Reporting the II values or the relevant DDG cycles for each benchmark in Table 1 would make this statement verifiable.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: SILVIA's DSP-packing claims rest on external packing methods and measured baselines, not on its own conclusions; the only same-group citation (NN2FPGA) is a baseline, not load-bearing.

full rationale

The central claim—that an LLVM pass can automatically identify packable add/mul/MAD operations and replace them with DSP-packed calls—is an implemented transformation validated against measured post-implementation reports. The packing schemes are imported from independent prior work (Fu et al. [5]; FINN [20]), not from the authors' own conclusions; the novel 4-bit unsigned packing in Sec. 2.3 is explicitly derived from bit-level product identities (Eq. 4), not assumed. The DSP savings are measured resource counts from Vivado, and the operation-density metric is a direct output of tuple sizes, not a fitted parameter renamed as a prediction. The CNN comparison against NN2FPGA [12] is the only same-group citation, but it is used as a baseline benchmark and does not justify the transformation's correctness or the savings claim; the load-bearing correctness assumption (functional equivalence of the custom RTL replacement in Sec. 3.4) is an unverified engineering premise, which is a correctness risk rather than a circular step. No equation or claim in the paper reduces to its own input by construction.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The paper contributes no new physical entities or fitted parameters; it relies on documented DSP capabilities and prior packing methods. The main unverified assumptions are the correctness of the custom RTL replacement and the representativeness of the benchmarks. The free parameters are user-selected configuration options that affect the reported results.

free parameters (2)
  • MAX_CHAIN_LEN = 3
    User-specified maximum DSP chain length; set to 3 in the experiments, trading logic vs memory resources.
  • OP_SIZE = 12/24 bits for additions; 4/8 bits for multiplications
    User-selected maximum operand width for packing; determines which operations are candidates.
assumptions (4)
  • domain assumption The AMD UltraScale/Versal DSP slice supports SIMD add/sub and the packing patterns of Fu et al. and Preusser/Branca exactly as described in Section 2.
    Section 2.1-2.3 relies on DSP datasheet behavior and prior packing designs without independent verification in this paper.
  • domain assumption The custom RTL modules replacing placeholder functions in Section 3.4 are functionally equivalent to the original scalar operations.
    Section 3.4 describes a re-implemented 'black box' replacement; a bug here would break all designs.
  • domain assumption The ALAP reordering and alias analysis in Section 3.2.1 preserve the program's semantics.
    The paper uses LLVM's memory aliasing infrastructure and conservatively assumes function calls may alias.
  • domain assumption The benchmarks are representative of compute-intensive HLS designs.
    Section 4 draws general conclusions from 11 benchmarks and two CNN frameworks.

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Cite this review

Pith. "Pith review of SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators." pith.science (2026). https://pith.science/paper/BYJZH263

@misc{pith2026241111384,
  author       = {Pith},
  title        = {Pith review of: SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BYJZH263}},
  note         = {Machine review of arXiv:2411.11384}
}
read the original abstract

High-level synthesis (HLS) aims at democratizing custom hardware acceleration with highly abstracted software-like descriptions. However, efficient accelerators still require substantial low-level hardware optimizations, defeating the HLS intent. In the context of field-programmable gate arrays, digital signal processors (DSPs) are a crucial resource that typically requires a significant optimization effort for its efficient utilization, especially when used for sub-word vectorization. This work proposes SILVIA, an open-source LLVM transformation pass that automatically identifies superword-level parallelism within an HLS design and exploits it by packing multiple operations, such as additions, multiplications, and multiply-and-adds, into a single DSP. SILVIA is integrated in the flow of the commercial AMD Vitis HLS tool and proves its effectiveness by packing multiple operations on the DSPs without any manual source-code modifications on several diverse state-of-the-art HLS designs such as convolutional neural networks and basic linear algebra subprograms accelerators, reducing the DSP utilization for additions by 70 % and for multiplications and multiply-and-adds by 50 % on average.

Figures

Figures reproduced from arXiv: 2411.11384 by the authors.

Figure 1
Figure 1. Given a loop computing two multiplications in parall [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. The modified high-level synthesis workflow with SIL [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. The bit mapping of the proposed method for computing fo [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (6 more)
Figure 2
Figure 2. Figure 2: With this approach, SILVIA processes an IR that is alr [PITH_FULL_IMAGE:figures/full_fig_p005_2.png]
Figure 4
Figure 4. Figure 4: The C code defined in Fig. 1a compiles to the LLVM code (a) where the two mul instructions (i.e., c0 and c1) are incompatible for vectorization since c0 is used before the definition of c1. SILVIA rearranges the code (b) to make c0 and c1 compatible, by moving the uses…
Figure 5
Figure 5. Figure 5: Example of an edge-case design where packing multipl [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 6
Figure 6. Figure 6: Modifications to the Vitis HLS synthesis script for e [PITH_FULL_IMAGE:figures/full_fig_p010_6.png]
Figure 7
Figure 7. Figure 7: The DSP utilization of the different benchmarks, norm [PITH_FULL_IMAGE:figures/full_fig_p012_7.png]
Figure 8
Figure 8. Figure 8: The convolutional neural network inference acceler [PITH_FULL_IMAGE:figures/full_fig_p014_8.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

30 extracted references · 29 canonical work pages

  1. [1]

    Nicolas Bohm Agostini, Serena Curzel, Vinay Amatya, Che ng Tan, Marco Minutoli, Vito Giovanni Castellana, Joseph Ma nzano, David Kaeli, and Antonino Tumeo. 2022. An MLIR-based Compiler Flow for Syste m-Level Design and Hardware Acceleration. In 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) . Association for Computing Machinery, N...

    work page 2022

  2. [2]

    Vicki H Allan, Reese B Jones, Randall M Lee, and Stephen J A llan. 1995. Software pipelining. ACM Comput. Surv. 27, 3 (9 1995), 367–432. https://doi.org/10.1145/212094.212131

    work page arXiv 1995

  3. [3]

    Versal ACAP DSP Engine Architecture Manual (AM004)

    AMD 2022. Versal ACAP DSP Engine Architecture Manual (AM004) . AMD. https://docs.amd.com/r/en-US/am004-versal-dsp- engine

    work page 2022

  4. [4]

    Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, A hmed Kammoona, Jason H Anderson, Stephen Brown, and Tomasz C zajkowski. 2011. LegUp: high-level synthesis for FPGA-based processor/acc elerator systems. In Proceedings of the 19th ACM/SIGDA International Symposium o n Field-Programmable Gate Arrays. Association for Computing Machinery, New York, NY,...

    work page 2011

  5. [5]

    Yao Fu, Ephrem Wu, Ashish Sirasao, Sedny Attia, Kamran Kh an, and Ralph Wittig. 2017. Deep Learning with INT8 Optimization on Xilinx Devices . Xilinx. https://japan.origin.xilinx.com/content/dam/ xilinx/support/documents/white_papers/wp486-deep-learning-int8.pdf

    work page 2017

  6. [6]

    Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Tak ada, and Katsuya Ishii. 2008. Chstone: A benchmark program suite for practical c-based high-level synthesis. In 2008 IEEE International Symposium on Circuits and Systems ( ISCAS). IEEE, Piscataway, NJ, USA, 1192–1195

    work page 2008

  7. [7]

    Free Software Foundation Inc. 2023. Auto-vectorization in GCC . Free Software Foundation Inc. Retrieved June 6, 2024 from https://gcc.gnu.org/projects/tree-ssa/vectorization .html

    work page 2023

  8. [8]

    Lana Josipović, Radhika Ghosal, and Paolo Ienne. 2018. D ynamically Scheduled High-level Synthesis. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays . Association for Computing Machinery, New York, NY, USA, 12 7–136

    work page 2018

Show all 30 references
  1. [9]

    Jindong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, and Yi Zeng. 2023. Firefly: a high-throughput hardware accelera tor for spiking neural networks with efficient DSP and memory optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Sy stems 31, 8 (2023), 1178–1191

    2023

  2. [10]

    Qi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, and Zeke W ang. 2023. SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low- Precision CNN on FPGAs. In 2023 International Conference on Field Programmable Techno logy (ICFPT). IEEE, Piscataway, NJ, USA, 161–169

    2023

  3. [11]

    Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yan g, Ying Wang, Huawei Li, and Xiaowei Li. 2023. DeepBurning-M ixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. In 2023 IEEE/ACM International Conference on Computer Aided D esign ...

    2023

  4. [12]

    Lazarescu, an d Luciano Lavagno

    Filippo Minnella, Teodoro Urso, Mihai T. Lazarescu, an d Luciano Lavagno. 2023. Design and Optimization of Residual Neural Network Accelerators for Low-Power FPGAs Using High-Level Synthesis. arXiv:230 9.15631 [cs.AR] Manuscript submitted to ACM 16 Giovanni Brignone, Roberto B...

    2023

  5. [13]

    Fabrizio Ottati. 2024. Efficient Deep Learning Inference: A Digital Hardware Perspec tive-Evaluating and improving performance and efficiency of artificial and spiking neural networks hardware accelerato rs. Ph. D. Dissertation. Politecnico di Torino

    2024

  6. [14]

    Preusser and Thomas A

    Thomas B. Preusser and Thomas A. Branca. 2020. Vectoriz ation of wide integer data paths for parallel operations wit h side-band logic monitoring the numeric overflow between vector lanes. US Patent 10,671, 388

    2020

  7. [15]

    Rishov Sarkar, Stefan Abi-Karam, Yuqi He, Lakshmi Sath idevi, and Cong Hao. 2023. FlowGNN: A Dataflow Architecture f or Real-Time Workload- Agnostic Graph Neural Network Inference. In 2023 IEEE International Symposium on High-Performance Comp uter Architecture (HPCA) . IEEE, Pi...

    2023

  8. [16]

    Akif Özkan, Oliver Keszocze, and Jürgen Teich

    Jan Sommer, M. Akif Özkan, Oliver Keszocze, and Jürgen Teich. 2022. DSP-Packin g: Squeezing Low-precision Arithmetic into FPGA DSP Blocks . In 2022 32nd International Conference on Field-Programmable L ogic and Applications (FPL) . IEEE, Piscataway, NJ, USA, 160–166

    2022

  9. [17]

    Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel S. Em er. 2017. Efficient Processing of Deep Neural Networks: A Tuto rial and Survey. Proc. IEEE 105, 12 (2017), 2295–2329. https://doi.org/10.1109/JPRO C.2017.2761740

    2017

  10. [18]

    LLVM team. 2012. LLVM 3.1 Release Notes . LLVM team. Retrieved May 5, 2024 from https://releases.ll vm.org/3.1/docs/ReleaseNotes.html

    2012

  11. [19]

    LLVM team. 2024. Auto-Vectorization in LLVM. LLVM team. Retrieved June 6, 2024 from https://llvm.org/d ocs/Vectorizers.html

    2024

  12. [20]

    Fraser, Giulio Gambardell a, Michaela Blott, Philip Leong, Magnus Jahre, and Kees Viss ers

    Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardell a, Michaela Blott, Philip Leong, Magnus Jahre, and Kees Viss ers. 2017. FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. In Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programm...

    2017

  13. [21]

    Convolutional Neural Network with INT4 Optimization on Xil inx Devices

    Xilinx 2020. Convolutional Neural Network with INT4 Optimization on Xil inx Devices . Xilinx. https://docs.amd.com/v/u/en-US/wp521-4bit-optimizat ion

    2020

  14. [22]

    UltraScale Architecture DSP Slice

    Xilinx 2021. UltraScale Architecture DSP Slice. Xilinx. https://docs.amd.com/v/u/en-US/ug579-ultras cale-dsp

    2021

  15. [23]

    Xilinx. 2024. HLS. https://github.com/Xilinx/HLS. A ccessed: 2024-05-04

    2024

  16. [24]

    Xilinx. 2024. Vitis HLS Introductory Examples. https: //github.com/Xilinx/Vitis-HLS-Introductory-Examples . Accessed: 2024-05-04

    2024

  17. [25]

    Xilinx. 2024. Vitis Libraries. https://github.com/X ilinx/Vitis_Libraries. Accessed: 2024-05-04

    2024

  18. [26]

    Jinho Yang, Sungwoong Yune, Sukbin Lim, Donghyuk Kim, a nd Joo-Young Kim. 2024. ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC...

    2024

  19. [27]

    Hanchen Ye, HyeGang Jun, Hyunmin Jeong, Stephen Neuend orffer, and Deming Chen. 2022. ScaleHLS: a scalable high-lev el synthesis framework with multi-level transformations and optimizations: invi ted. In Proceedings of the 59th ACM/IEEE Design Automation Conferen ce. Associatio...

    2022

  20. [28]

    Jingwei Zhang, Meng Zhang, Xinye Cao, and Guoqing Li. 20 23. Uint-Packing: Multiply Your DNN Accelerator Performan ce via Unsigned Integer DSP Packing. In 2023 60th ACM/IEEE Design Automation Conference (DAC) . Association for Computing Machinery, New York, NY, USA, 1– 6

    2023

  21. [29]

    Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Mia o Hu, and Wenfeng Zhao. 2022. Wsq-addernet: Efficient weight s tandardization based quantized addernet fpga accelerator design with high-density int8 dsp-lut co-packing optimization. InProceedings of the 41st IEEE/ACM Inter...

    2022

  22. [30]

    Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, an d Jason Cong. 2013. Improving high level synthesis optimiza tion opportunity through polyhedral transformations. In Proceedings of the ACM/SIGDA International Symposium on Fie ld Programmable Gate Arrays . Association f...

    2013

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