A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling

Alexandra Dickie; Andre Saraiva; Andrew S. Dzurak; Arne Laucht; Chih Hwan Yang; Christopher C. Escott; Fay E. Hudson; Jes\'us D. Cifuentes; Jonathan Yue Huang; Kok Wai Chan

REVIEW 3 major objections 5 minor 1 cited by

A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read The paper demonstrates a 2×2 silicon MOS array with voltage-tunable tunnel coupling on every nearest-neighbor pair, up to 30 decades per volt, and predicts all but one pair meet the exchange-control rate needed for spin-qubit gates.

desk verdict A real 2x2 MOS dot array with interstitial gates, but the abstract oversells the tunnel-control claim: J12 is qualitative, and the 30 dec/V figure is one gate only. read the letter →

arxiv 2411.13882 v3 pith:FR67LNP6 submitted 2024-11-21 cond-mat.mes-hall quant-ph

Wee Han Lim , Tuomo Tanttu , Tony Youn , Jonathan Yue Huang , Santiago Serrano , Alexandra Dickie , Steve Yianni , Fay E. Hudson

show 7 more authors

Christopher C. Escott Chih Hwan Yang Arne Laucht Andre Saraiva Kok Wai Chan Jesús D. Cifuentes Andrew S. Dzurak

This is my paper · ORCID

classification cond-mat.mes-hallquant-ph PACS 73.21.La85.35.Gv03.67.Lx

keywords siliconquantumdotsMOStunabilitytunnelcouplings2Ddotarrayexchangeinteractionspinqubits

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims a 2×2 silicon metal-oxide-semiconductor (MOS) quantum dot array in which every neighboring pair of dots has a voltage-tunable tunnel coupling, controlled by a dedicated interstitial exchange gate. This matters because previous silicon MOS 2D dot arrays had not demonstrated tunable coupling across all adjacent pairs, and 2D arrays are a necessary step toward error-correctable surface-code spin qubit processors. At 4.2 K the device forms isolated double-dot and triple-dot configurations in every orientation, and direct tunnel-rate measurements show control rates up to 30 decades per volt, with lower rates for gates placed in higher metal layers. The paper further argues that tunnel-rate controllability measured at 4 K predicts exchange controllability, allowing devices to be screened for two-qubit gate suitability without millikelvin spin measurements.

What carries the argument

The load-bearing element is the interstitial exchange gate, a narrow electrode placed between two plunger gates that raises or lowers the interdot potential barrier and thereby controls the tunnel coupling $t$. The argument is carried by the four-layer gate stack in which each J-gate sits at a different height (J23 in layer 1, J12/J34 in layer 3, J41 in layer 4), so the measured 30.2/10.4/2.5 decades-per-volt control rates map directly onto gate geometry. The quantitative bridge from tunnel to exchange control is the approximate identity $d\log_{10}(J)/dV_J \approx 2\,d\log_{10}(t)/dV_J$, which follows from the Hund–Mulliken estimate $J\approx 4t^2/U$ and is supported here by path-integral simulations and prior experimental data; it converts the 4.2 K tunnel measurements into predicted exchange-control rates without requiring millikelvin spin measurements.

What would settle it

Cool this exact 2×2 device to millikelvin, form spin qubits in the P2–P3 and P3–P4 pairs, and measure the exchange splitting $J$ as a function of $V_{J23}$ and $V_{J34}$ via coherent two-qubit oscillations; then compare the measured $d\log_{10}(J)/dV_J$ with twice the tunnel-control rates from Fig. 3(d). If the ratio is not close to 2 across the operating range, the predicted exchange rates (60 and 21 decades per volt) and the screening claim would fail.

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Extended reading notes

Core claim

The paper reports a 2×2 quantum dot array in a silicon MOS gate stack, with four dots formed under plunger gates P1–P4 and one interstitial exchange (J) gate controlling the tunnel barrier between every neighboring pair: J12, J23, J34, and J41. At 4.2 K, charge stability diagrams show well-defined double-dot and triple-dot charge configurations in all four pairwise orientations, demonstrating that each pair can be isolated and operated in the few-electron regime. Direct tunnel-rate measurements give control rates of 30.2±4.9 decades per volt for J23, 10.4±0.7 for J34, and 2.5±0.2 for J41, with J12 sharing the layer-3 geometry of J34; the spread is attributed to the J-gates sitting at different heights and cross-sectional profiles in the four-layer stack. Using the relation $d\log_{10}(J)/dV_J \approx 2\,d\log_{10}(t)/dV_J$, the paper predicts exchange control rates of about 60, 21, and 5 decades per volt for those gates, concluding that only J41 falls below the roughly 8 decades per volt thought necessary for switching entanglement on and off, and proposing an increased P1–P4 pitch to improve J41.

Load-bearing premise

The argument's load-bearing assumption is that a change in exchange-gate voltage moves the exchange interaction between two dots about exactly twice as fast as it moves the tunnel coupling, a relation that comes from a simple model and is supported here by previous experiments and simulations rather than by direct exchange measurements on this device.

Editorial extensions

If this is right

A 2×2 silicon MOS dot array can be operated in the few-electron regime in every nearest-neighbor pair, with both double-dot and triple-dot configurations formed and isolated at 4.2 K.
The interstitial gate J23, placed in the lowest metal layer with the widest geometry, tunes the P2–P3 tunnel coupling at 30.2±4.9 decades per volt, the strongest control demonstrated.
Tunnel control rates of 10.4 and 2.5 decades per volt for J34 and J41 imply exchange control rates of about 21 and 5 decades per volt, so only J41 falls below the roughly 8 decades per volt threshold regarded as needed for reliable entanglement switching.
Measuring tunnel-rate controllability at 4.2 K can predict whether a device meets exchange controllability requirements without dilution refrigeration.
Charge sensing visibility is highest for dot pairs perpendicular to the SET current axis, which guides where the charge sensor should be placed relative to the array.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the 4.2 K tunnel-control screening is adopted, the same measurement could be extended to all four J-gates in future devices as a pass/fail test against the 8 decades-per-volt exchange threshold before spending dilution-refrigerator time.
The systematic loss of tunability for gates in higher metal layers (J41 worst, J23 best) suggests a design rule: place exchange gates as close to the channel as fabrication allows, or increase plunger pitch where high-layer gates are unavoidable; the paper's own simulation points to the pitch lever.
Because the J-gates that form unintended dots at high voltage (J12, J23, J34) define an upper bound on usable exchange bias, an unexplored practical consequence is that the usable tuning window, not just the dec/V slope, will constrain two-qubit gate calibration.
A testable extension of the screening method would be to compare the 4.2 K tunnel-rate prediction against direct exchange spectroscopy from coherent two-qubit gates in the same 2×2 device, which the paper did not perform.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

First thing to know: this paper is a genuine engineering step — a 2x2 silicon MOS dot array with interstitial exchange gates in a four-layer stack, showing pairwise charge stability for all four edges and quantitative tunnel-rate control for three of the four gates. That is new for MOS; prior 2D MOS arrays did not show this. The authors also use their path-integral simulations to connect tunnel-rate lever arms to exchange control, which is useful design guidance. The abstract, however, overstates the result. The 'all nearest-neighbor tunnel couplings' claim is supported quantitatively for J23, J34, J41 only; J12 is shown qualitatively via the charge stability diagram but no tunnel-rate curve is reported. The 'up to 30 decades per volt' is a single-gate maximum (J23). That matters for the headline. The stress-test note is correct on this point, and it is not a manufactured flaw: the text explicitly says 'we repeat the same measurement on J23, J34 and J41,' omitting J12.

The exchange-rate conversion via Eq. B1 is an approximation (J ≈ 4t^2/U). The authors support it with their own simulations and prior experimental work; it is not circular, but it is model-based. The predicted 5, 21, 60 dec/V exchange rates carry no error bars, and the conclusion that only J41 falls below threshold depends on that approximation. That is a real limitation, though a moderate one.

The writing is clear, the figures are informative, and the authors are honest about J-dot formation and the SET sensitivity issues. They also note that simulations underestimate the measured tunnel control rates, which is candid. Missing: J12 rate data, error propagation, and a proper data/code release (the 'available upon reasonable request' boilerplate is weak). These are fixable in revision. If the authors either measure J12 or explicitly state that the all-pair claim is qualitative for that edge, and if they add uncertainty estimates for the exchange rates, the paper would be solid. As it stands, the core device demonstration is credible and valuable, but the abstract needs to be reined in.

I'd send this to a serious referee. It is a worthwhile device paper for the spin-qubit community, and the missing J12 point is exactly the kind of thing a referee should catch. For my own reading group, I'd probably mention it as an example of how device papers live and die by their claims.

Referee Report

3 major / 5 minor

Summary. This paper reports a 2×2 silicon metal-oxide-semiconductor (MOS) quantum dot array in which each nearest-neighbor pair is coupled through an interstitial exchange (J) gate, defined in a four-layer aluminum gate stack. At 4.2 K the authors demonstrate isolated-mode double-dot charge stability diagrams for all four pairs and triple-dot configurations for all four triples. Gate-pulsed lock-in measurements of interdot tunnel rates yield exponential control slopes of 30.2±4.9 dec/V for J23, 10.4±0.7 dec/V for J34, and 2.5±0.2 dec/V for J41; no quantitative tunnel-rate data are reported for the fourth pair (J12). Using the relation dlog10(J)/dV_J ≈ 2 dlog10(t)/dV_J (Appendix B), the authors estimate exchange control rates of 60, 21, and 5 dec/V, and conclude that only the J41 pair falls below the ~8 dec/V controllability benchmark. The manuscript claims this is the first silicon MOS 2D array with demonstrated tunable tunnel coupling between all adjacent dot pairs.

Significance. The device itself is a real advance with strong supporting evidence: clean few-electron stability diagrams for every adjacent pair, four different triple-dot configurations, three quantitative tunnel-rate control curves with a coherent and well-explained layer-dependent hierarchy (J23 > J34 > J41), a fabrication-aware simulation pipeline, and falsifiable quantitative predictions (exchange control rates of 5, 21, and 60 dec/V; only J41 below the 8 dec/V threshold) that can be tested at millikelvin temperatures. The authors also deserve credit for disclosing the limitations of their own evidence, including the qualitative-only agreement of the simulations and the model dependence of Eq. (B1). The weakness of the paper is that its headline claims overstate that evidence: the title and abstract assert fully tunable coupling for all pairs and 'up to 30 decades per volt,' while the data support quantitative control rates for only three of the four pairs, with the maximum realized on a single gate. Those calibration issues are fixable by adding the J12 dataset or rewording the claims, and I do not see a defect in the core device demonstration.

major comments (3)

[Abstract; Section IV; Fig. 3] The paper's central claim is supported by quantitative data for only three of the four nearest-neighbor pairs. Section IV states 'We repeat the same measurement on J23, J34 and J41' and Fig. 3(d) shows fitted tunnel-rate control slopes for exactly these three gates (30.2±4.9, 10.4±0.7, and 2.5±0.2 dec/V); no tunnel-rate data are presented for J12. For P1–P2, Fig. 2(a) offers only qualitative evidence: the charge-transition visibility decreases as VJ12 is reduced, and for VJ12 > 1 V the J12 gate itself forms an unintended dot, so the demonstrated tuning range for that pair is, at best, one-directional. The abstract's claim of 'control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt' and the title's 'fully tuneable pairwise interdot coupling' therefore exceed the measurements. Note also that the 30 dec/V figure is the single best gate (J23), with the other two measured gates at 10.4 and 2.5 dec/V. The authors should either supply the missing J12 tunnel-rate measurement or revise the title, abstract, and conclusion to state that quantitative tunnel-rate control is demonstrated for three pairs and qualitative tunability (with a J-dot limitation) for the fourth, with measured slopes spanning approximately 2.5–30 dec/V.
[Appendix B, Eq. (B1); Section IV] The exchange-control predictions (5, 21, 60 dec/V) and the conclusion that only J41 falls below the ~8 dec/V threshold rest on Eq. (B1), dlog10(J)/dV_J ≈ 2 dlog10(t)/dV_J, which is derived from the Hund-Mulliken relation J ≈ 4t²/U. The authors correctly disclose that this estimate 'may break down under strong interaction regimes,' and their path-integral support is admittedly only in qualitative agreement: the simulated tunnel control rates are 'significantly lower than experimental results' (caption of Fig. 7). In light of those self-stated caveats, the claims in Appendix B that tunnel-rate controllability 'can serve as an effective predictor' of exchange controllability, and in the Conclusion that the design ensures 'high-level exchange controllability,' are stated more firmly than the evidence. Please either present the exchange predictions as explicitly conditional on Eq. (B1) holding for this device geometry, or provide a quantitative validation of Eq. (B1) (for example, the same-device tunnel-versus-exchange comparison from Ref. [6]).
[Section IV (Fig. 3); Appendix B] The measured observable in Fig. 3 is the interdot electron tunnel rate r (y-axis in Hz), but Section IV and Eq. (B1) treat the fitted slopes as control rates of the tunnel coupling t ('tunnel control rates dlog10(t)/dV_J'). These are not the same quantity: for incoherent interdot tunneling the rate scales approximately as r ∝ t² (Fermi's golden rule), so if the prefactor is weakly voltage-dependent over the measured range then dlog10(r)/dV_J ≈ 2 dlog10(t)/dV_J. Under that standard assumption the reported control slopes (30.2, 10.4, 2.5 dec/V) are a factor of two larger than the tunnel-coupling control slopes, and the exchange rates obtained from Eq. (B1) would be 30, 10, and 2.5 dec/V rather than 60, 21, and 5 dec/V (the qualitative 'only J41 below threshold' conclusion would be unchanged). Since the relation between r and t is never stated, please clarify it; if a golden-rule conversion applies, the claims should consistently refer to control of interdot tunnel rates, with the tunnel-coupling and exchange slopes adjusted accordingly.

minor comments (5)

[Supplementary Figs. 5–7; main text Figs. 1–3] The diagonal gate between P1 and P4 is labelled 'J41' in the main text but 'J14' in the supplementary simulation figures; please use one label consistently, particularly since Figs. 3(d) and 7(c)–(d) are directly compared.
[Section IV; Fig. 3(c)] The stretched-exponential fit ΔID(f) = ID exp[(−f/r)^n] includes a stretch exponent n, but no fitted n values are reported for any of the three datasets; please report n with its uncertainty, since the extracted r depends on n.
[Section IV] The exchange control rates (5, 21, 60 dec/V) are quoted without uncertainties; propagating the stated tunnel-rate fit errors (0.2, 0.7, 4.9 dec/V) would clarify how robust the threshold conclusion is.
[Figure captions; manuscript assembly] Several figure captions are garbled or duplicated in the manuscript text: the caption of Fig. 5 repeats the caption of Fig. 2, the caption of Fig. 3 contains a stray sentence about sweeping 'J1 and step frequency,' and the captions of Figs. 6–7 contain redundant fragments. These assembly problems should be fixed in revision.
[Introduction; Refs. [19,44,45]] The novelty statement that 'none have yet demonstrated tunnel coupling control between all quantum dot pairs' in silicon MOS should be verified against the most recent literature, including the 2024/2025 works already cited by the authors (Refs. [19,44,45]); if any of those report interdot coupling control in MOS or compatible arrays, the claim needs qualification.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central tunnel-coupling measurements are direct, and the exchange-rate estimates are model-based extrapolation with independent benchmarks.

full rationale

The paper's central claim—voltage-tunable nearest-neighbor tunnel coupling in a 2x2 MOS dot array—rests on direct charge-stability and lock-in frequency measurements, not on any fitted parameter or self-referential definition. The only derived quantity is the exchange control rate, obtained from Eq. (B1), dlog10(J)/dVJ ≈ 2 dlog10(t)/dVJ, which follows from the Hund-Mulliken relation J ≈ 4t^2/U. The paper explicitly discloses this approximation and supports it with prior simultaneous tunnel/exchange measurements [6] and path-integral simulations [37,40] benchmarked against Full CI [40]; this is model-based extrapolation with external anchors, not a parameter fitted to reproduce the claimed exchange rates. No step of the derivation is equivalent to its inputs by construction. Concerns that J12 lacks a quantitative tunnel-rate measurement or that Eq. (B1) may overestimate strong-interaction exchange rates are completeness and validity issues, not circularity.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central experimental claim depends on standard charge sensing and stability diagram interpretation plus the nominal identity of the imaged and measured devices. The exchange predictions additionally depend on a model relation and simulation method, both validated mostly in the authors' prior work. No new entities or unusual postulates are introduced.

free parameters (2)

stretch exponent n in tunnel-rate fit = not reported
Tunnel rates are extracted by fitting ΔID(f) = ID exp[(-f/r)^n] (Section IV). The value of n is not stated, and it affects the extracted r and the resulting control slopes.
device-geometry parameters for simulations = tuned to SEM
Appendix A states that simulation parameters used to generate the 3D geometry are carefully tuned to match SEM images; these parameters are not independently measured and affect the simulation trends in Figs. S2-S4.

assumptions (4)

domain assumption Standard quantum dot charge stability interpretation: each transition line in a stability diagram corresponds to a change in electron occupancy and interdot tunneling.
Used in Section III to infer double-dot and triple-dot configurations from SET current maps.
domain assumption Hund-Mulliken relation J ≈ 4t^2/U and its derivative dlog10(J)/dVJ ≈ 2 dlog10(t)/dVJ.
Appendix B uses this to estimate exchange control rates from measured tunnel control rates; the paper notes possible breakdown in strong-interaction regimes and cites prior validation.
domain assumption Validity of the path-integral simulation method [37,40] for tunnel and exchange couplings in the strongly interacting regime.
Used in Appendix A and Fig. S3 to support the gate-layer-dependent tunability trend and Eq. B1; benchmarked against Full CI and experiments in the cited works.
domain assumption The SEM image in Fig. 1a represents a device nominally identical to the measured one.
All geometric arguments about gate shape and layer position rely on this nominal identity, since no TEM of the measured device is presented.

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Cite this review

Pith. "Pith review of A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling." pith.science (2026). https://pith.science/paper/FR67LNP6

@misc{pith2026241113882,
  author       = {Pith},
  title        = {Pith review of: A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FR67LNP6}},
  note         = {Machine review of arXiv:2411.13882}
}

read the original abstract

Recent advances in semiconductor spin qubits have achieved linear arrays exceeding ten qubits. Moving to two-dimensional (2D) qubit arrays is a critical next step to advance towards fault-tolerant implementations, but it poses substantial fabrication challenges, particularly because enabling control of nearest-neighbor entanglement requires the incorporation of interstitial exchange gates between quantum dots in the qubit architecture. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all adjacent dots. The device is characterized at 4.2 K, where we demonstrate the formation and isolation of double-dot and triple-dot configurations. We show control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt through the interstitial exchange gates and use advanced modeling tools to estimate the exchange interactions that could be realized among qubits in this architecture. These results represent a significant step towards the development of 2D MOS quantum processors compatible with foundry manufacturing techniques.

Figures

Figures reproduced from arXiv: 2411.13882 by the authors.

**Figure 2.** (a) Falsecolored scanning electron microscopy (SEM) image of an identi experiment(b) Schematic representation of the multigate stack deviceillustrat tunneling event occurs between the pairwise dots. (a) Charge stability diagram for the P1 [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** FIG. 3. Tunnel rates measurement between pairwise dots as a function of J-gate voltage, [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (4 more)

**Figure 4.** Figure 4: FIG. 4. Isolated-mode triple dot charge stability diagrams in four different configurations. Triple dot system of (a) P1 [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]

**Figure 5.** Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]

**Figure 7.** Figure 7: FIG. 7 [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]

**Figure 8.** Figure 8: FIG. 8. Simulation of the dependence of the exchange control rate on the inter-dot pitch. This simulation uses a simplified two [PITH_FULL_IMAGE:figures/full_fig_p011_8.png]

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Works this paper leans on

45 extracted references · 29 canonical work pages · cited by 1 Pith paper

[6]

Tanttu, W

T. Tanttu, W. H. Lim, J. Y. Huang, N. Dumoulin Stuyck, W. Gilbert, R. Y. Su, M. Feng, J. D. Cifuentes, A. E. Seedhouse, S. K. Seritan,et al., Assessment of the errors of high-fidelity two-qubit gates in silicon quantum dots, Nature Physics , 1 (2024)

work page 2024
[1]

M. T. Mądzik, S. Asaad, A. Youssry, B. Joecker, K. M. Rudinger, E. Nielsen, K. C. Young, T. J. Proctor, A. D. Baczewski, A. Laucht, V. Schmitt, F. E. Hudson, K. M. Itoh, A. M. Jakob, B. C. Johnson, D. N. Jamieson, A. S. Dzurak, C. Ferrie, R. Blume-Kohout, and A. Morello, Precision tomography of a three-qubit donor quantum processor in silicon, Nature601, ...

2022
[2]

X. Xue, M. Russ, N. Samkharadze, B. Undseth, A. Sam- mak, G. Scappucci, and L. M. K. Vandersypen, Quantum logic with spin qubits crossing the surface code threshold, Nature601, 343 (2022)

2022
[3]

7.a-b,Path integral Monte Carlo simulations ofa)tunnel couplings andb)exchange couplings as a function of J-gate biasing in the model of FIG

A.Noiri, K.Takeda, T.Nakajima, T.Kobayashi, A.Sam- 10 P4 J14 P1 P4 P2 P3J34 J12 SET a -60 0 60 Position (nm) Electron Potential (eV) 0.0 0.5 1.0 1.5 -60 0 60 -0.1 -1.1 -0.6 -0.1 P2 P3 P1 P4 P1 P2 𝑽𝑽𝑱𝑱 (V) J12 J14 J34 J23 -1.1 -0.6 Electrostatic Simulations a Si SiO2 Path Integral Simulation of Tunnel and Exchange Rates P3 J14J34J12J23 Layer 1 Layer 3 Laye...

work page 2022
[4]

A. R. Mills, C. R. Guinn, M. J. Gullans, A. J. Sigillito, M. M. Feldman, E. Nielsen, and J. R. Petta, Two-qubit silicon quantum processor with operation fidelity exceed- ing 99%, Science Advances8, eabn5130 (2022)

2022
[5]

A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. H. Fong, S. D. Ha, D. R. Hulbert, C. A. C. Jack- son, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Universal logic with en- coded spin qubits in silic...

2023
[7]

Petit, J

L. Petit, J. M. Boter, H. G. J. Eenink, G. Droulers, M. L. V. Tagliaferri, R. Li, D. P. Franke, K. J. Singh, J. S. Clarke, R. N. Schouten, V. V. Dobrovitski, L. M. K. Vandersypen, and M. Veldhorst, Spin lifetime and charge noise in hot silicon quantum dot qubits, Physical Review Letter121, 076801 (2018)

work page 2018
[8]

C. H. Yang, R. C. C. Leon, J. C. C. Hwang, A. Saraiva, T. Tanttu, W. Huang, J. Camirand Lemyre, K. W. Chan, K. Y. Tan, F. E. Hudson, K. M. Itoh, A. Morello, M. Pioro-Ladrière, A. Laucht, and A. S. Dzurak, Oper- ation of a silicon quantum processor unit cell above one kelvin, Nature580, 350 (2020)

2020

Show all 45 references

[9]

Petit, H

L. Petit, H. G. J. Eenink, M. Russ, W. I. L. Lawrie, N. W. Hendrickx, S. G. J. Philips, J. S. Clarke, L. M. K. Vandersypen, and M. Veldhorst, Universal quantum logic in hot silicon qubits, Nature580, 355 (2020)

2020
[10]

L. C. Camenzind, S. Geyer, A. Fuhrer, R. J. Warbur- 11 53 57 61 Exchange control rate [Decades/V ] 4 6 8 P1 P2J Gate-to-gate pitch a b Gate-to-gate pitch [nm] FIG. 8. Simulation of the dependence of the exchange control rate on the inter-dot pitch. This simulation uses a simpl...

2022
[11]

J. Y. Huang, R. Y. Su, W. H. Lim, M. Feng, B. van Straaten, B. Severin, W. Gilbert, N. Dumoulin Stuyck, T. Tanttu, S. Serrano,et al., High-fidelity spin qubit op- eration and algorithmic initialization above 1 k, Nature 627, 772 (2024)

2024
[12]

S. G. Philips, M. T. Mądzik, S. V. Amitonov, S. L. de Snoo, M. Russ, N. Kalhor, C. Volk, W. I. Lawrie, D. Brousse, L. Tryputen,et al., Universal control of a six-qubit quantum processor in silicon, Nature609, 919 (2022)

2022
[13]

H. C. George, M. T. Ma¸dzik, E. M. Henry, A. J. Wag- ner, M. M. Islam, F. Borjans, E. J. Connors, J. Corrigan, M. Curry, M. K. Harper,et al., 12-spin-qubit arrays fab- ricated on a 300 mm semiconductor manufacturing line, Nano Letters 10.1021/acs.nanolett.4c05205 (2024)

2024 doi
[14]

A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, Surface codes: Towards practical large-scale quantum computation, Physical Review A - Atomic, Molecular, and Optical Physics86, 32324 (2012)

2012
[15]

Siegel, A

A. Siegel, A. Strikis, and M. Fogarty, Towards early fault tolerance on a 2×n array of qubits equipped with shut- tling, PRX Quantum5, 040328 (2024)

2024
[16]

Mukhopadhyay, J

U. Mukhopadhyay, J. P. Dehollain, C. Reichl, W. Wegscheider, and L. M. Vandersypen, A 2×2 quan- tum dot array with controllable inter-dot tunnel cou- plings, Applied Physics Letters112, 183505 (2018)

2018
[17]

Mortemousque, B

P.-A. Mortemousque, B. Jadot, E. Chanrion, V. Thiney, C. Bäuerle, A. Ludwig, A. D. Wieck, M. Urdampilleta, and T. Meunier, Enhanced spin coherence while displac- ing electron in a two-dimensional array of quantum dots, PRX Quantum2, 030331 (2021)

2021
[18]

F. K. Unseld, M. Meyer, M. T. Mądzik, F. Borsoi, S. L. de Snoo, S. V. Amitonov, A. Sammak, G. Scappucci, M. Veldhorst, and L. M. Vandersypen, A 2d quantum dot array in planar 28si/sige, Applied Physics Letters 123, 084002 (2023)

2023
[19]

Wang, J.-M

N. Wang, J.-M. Kang, W.-L. Lu, S.-M. Wang, Y.-J. Wang, H.-O. Li, G. Cao, B.-C. Wang, and G.-P. Guo, Highly tunable 2d silicon quantum dot array with cou- pling beyond nearest neighbors, Nano Letters24, 13126 (2024)

2024
[20]

C.-A. Wang, V. John, H. Tidjani, C. X. Yu, A. S. Ivlev, C.Déprez, F.vanRiggelen-Doelman, B.D.Woods, N. W. Hendrickx, W. I. Lawrie,et al., Operating semi- conductor quantum processors with hopping spins, Sci- ence385, 447 (2024)

2024
[21]

Borsoi, N

F. Borsoi, N. W. Hendrickx, V. John, M. Meyer, S. Motz, F. van Riggelen, A. Sammak, S. L. de Snoo, G. Scap- pucci, and M. Veldhorst, Shared control of a 16 semicon- ductor quantum dot crossbar array, Nature Nanotechnol- ogy19, 21 (2024)

2024
[22]

N.W.Hendrickx, W.I.Lawrie, M.Russ, F.vanRiggelen, S. L. de Snoo, R. N. Schouten, A. Sammak, G. Scappucci, andM.Veldhorst,Afour-qubitgermaniumquantumpro- cessor, Nature591, 580 (2021)

2021
[23]

Zhang, E

X. Zhang, E. Morozova, M. Rimbach-Russ, D. Jirovec, T.-K. Hsiao, P. C. Fariña, C.-A. Wang, S. D. Ooster- hout, A. Sammak, G. Scappucci,et al., Universal control of four singlet–triplet qubits, Nature Nanotechnology , 1 (2024)

2024
[24]

X. Xue, M. Russ, N. Samkharadze, B. Undseth, A. Sam- mak, G. Scappucci, and L. M. K. Vandersypen, Quantum logic with spin qubits crossing the surface code thresh- old, Nature601, 343 (2022), arXiv:2107.00628 [cond- mat, physics:quant-ph]

2022 arXiv
[25]

A. R. Mills, C. R. Guinn, M. J. Gullans, A. J. Sigillito, M. M. Feldman, E. Nielsen, and J. R. Petta, Two-qubit silicon quantum processor with operation fidelity exceed- ing 99%, ScienceAdvances8, eabn5130 (2022), publisher: American Association for the Advancement of Science

2022
[26]

N. D. Stuyck, A. Saraiva, W. Gilbert, J. C. Pardo, R. Li, C. C. Escott, K. De Greve, S. Voinigescu, D. J. Reilly, and A. S. Dzurak, Cmos compatibility of semi- conductor spin qubits, arXiv preprint arXiv:2409.03993 10.48550/arXiv.2409.03993 (2024)

2024 doi arXiv
[27]

Steinacker, N

P. Steinacker, N. D. Stuyck, W. H. Lim, T. Tanttu, M. Feng, A. Nickl, S. Serrano, M. Candido, J. D. Ci- fuentes, F. E. Hudson, K. W. Chan, S. Kubicek, J. Jus- sot, Y. Canvel, S. Beyne, Y. Shimura, R. Loo, C. God- frin, B. Raes, S. Baudot, D. Wan, A. Laucht, C. H. Yang, A. Sara...

2024 arXiv
[28]

Ishihara, A

L.M.K.Vandersypen, H.Bluhm, J.S.Clarke, A.S.Dzu- rak, R. Ishihara, A. Morello, D. J. Reilly, L. R. Schreiber, and M. Veldhorst, Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent, npj Quan- tum Information3, 34 (2017)

2017
[29]

Veldhorst, H

M. Veldhorst, H. G. J. Eenink, C. H. Yang, and A. S. Dzurak, Silicon cmos architecture for a spin-based quan- tum computer, Nature Communications8, 1766 (2017)

2017
[30]

Burkard, T

G. Burkard, T. D. Ladd, A. Pan, J. M. Nichol, and J. R. Petta, Semiconductor spin qubits, Reviews of Modern Physics95, 025003 (2023)

2023
[31]

Gilbert, A

W. Gilbert, A. Saraiva, W. H. Lim, C. H. Yang, A. Laucht, B. Bertrand, N. Rambal, L. Hutin, C. C. Escott, M. Vinet,et al., Single-electron operation of a silicon-cmos 2×2 quantum dot array with integrated charge sensing, Nano Letters20, 7882 (2020)

2020
[32]

J. Duan, M. A. Fogarty, J. Williams, L. Hutin, M. Vinet, and J. J. Morton, Remote capacitive sensing in two- dimensional quantum-dot arrays, Nano Letters20, 7123 (2020)

2020
[33]

Ansaloni, H

F. Ansaloni, H. Bohuslavskyi, F. Fedele, T. Rasmussen, B. Brovang, F. Berritta, A. Heskes, J. Li, L. Hutin, B. Venitucci,et al., Gate reflectometry in dense quantum dot arrays, New Journal of Physics25, 033023 (2023)

2023
[34]

S. J. Angus, A. J. Ferguson, A. S. Dzurak, and R. G. Clark, Gate-defined quantum dots in intrinsic silicon, Nano Letters7, 2051 (2007)

2007
[35]

W. H. Lim, F. A. Zwanenburg, H. Huebl, M. Möttönen, K. W. Chan, A. Morello, and A. S. Dzurak, Observation of the single-electron regime in a highly tunable silicon quantum dot, Applied Physics Letters95, 242102 (2009)

2009
[36]

W. H. Lim, H. Huebl, L. Willems van Beveren, S. Rubanov, P. Spizzirri, S. Angus, R. Clark, and A. Dzu- rak, Electrostatically defined few-electron double quan- tum dot in silicon, Applied Physics Letters94, 173502 (2009)

2009
[37]

J. D. Cifuentes, T. Tanttu, W. Gilbert, J. Y. Huang, E. Vahapoglu, R. C. Leon, S. Serrano, D. Otter, D. Dun- more, P. Y. Mai,et al., Bounds to electron spin qubit variability for scalable cmos architectures, Nature Com- munications15, 4299 (2024)

2024
[38]

C. H. Yang, W. H. Lim, N. S. Lai, A. Rossi, A. Morello, and A. S. Dzurak, Orbital and valley state spectra of a few-electron silicon quantum dot, Physical Review B86, 115319 (2012)

2012
[39]

Eenink, L

H. Eenink, L. Petit, W. Lawrie, J. Clarke, L. Vander- sypen, and M. Veldhorst, Tunable coupling and isolation of single electrons in silicon metal-oxide-semiconductor quantum dots, Nano letters19, 8653 (2019)

2019
[40]

J. D. Cifuentes, P. Y. Mai, F. Schlattner, H. E. Ercan, M. Feng, C. C. Escott, A. S. Dzurak, and A. Saraiva, Path-integral simulation of exchange interactions in cmos spin qubits, Physical Review B108, 155413 (2023)

2023
[41]

A. West, B. Hensen, A. Jouan, T. Tanttu, C.-H. Yang, A. Rossi, M. F. Gonzalez-Zalba, F. Hudson, A. Morello, D. J. Reilly, and A. S. Dzurak, Gate-based single-shot readout of spins in silicon, Nature Nanotechnology14, 437 (2019)

2019
[42]

S. M. Patomäki, J. Williams, F. Berritta, C. Lainé, M. A. Fogarty, R. C. C. Leon, J. Jussot, S. Kubicek, A. Chat- terjee, B. Govoreanu, F. Kuemmeth, J. J. L. Morton, and M. F. Gonzalez-Zalba, Elongated quantum dot as a distributed charge sensor, Phys. Rev. Appl.21, 054042 (2024)

2024
[43]

Vahapoglu, J

E. Vahapoglu, J. P. Slack-Smith, R. C. C. Leon, W. H. Lim, F. E. Hudson, T. Day, T. Tanttu, C. H. Yang, A. Laucht, A. S. Dzurak, and J. J. Pla, Single- electron spin resonance in a nanoelectronic device using a global field, Science Advances7, eabg9158 (2021), https://www.scie...

2021 doi
[44]

S. D. Ha, E. Acuna, K. Raach, Z. T. Bloom, T. L. Brecht, J. M. Chappell, M. D. Choi, J. E. Christensen, I. T. Counts, D. Daprano, J. P. Dodson, K. Eng, D. J. Fi- alkow, C. A. C. Garcia, W. Ha, T. R. B. Harris, nathan holman, I. Khalaf, J. W. Matten, C. A. Peterson, C. E. Plesh...

2025 arXiv
[45]

R. Li, V. Levajac, C. Godfrin, S. Kubicek, G. Simion, B. Raes, S. Beyne, I. Fattal, A. Loenders, W. D. Roeck, M. Mongillo, D. Wan, and K. D. Greve, A trilinear quantum dot architecture for semiconductor spin qubits (2025), arXiv:2501.17814 [quant-ph]

2025 arXiv

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [6]

Tanttu, W

T. Tanttu, W. H. Lim, J. Y. Huang, N. Dumoulin Stuyck, W. Gilbert, R. Y. Su, M. Feng, J. D. Cifuentes, A. E. Seedhouse, S. K. Seritan,et al., Assessment of the errors of high-fidelity two-qubit gates in silicon quantum dots, Nature Physics , 1 (2024)

work page 2024

[2] [1]

M. T. Mądzik, S. Asaad, A. Youssry, B. Joecker, K. M. Rudinger, E. Nielsen, K. C. Young, T. J. Proctor, A. D. Baczewski, A. Laucht, V. Schmitt, F. E. Hudson, K. M. Itoh, A. M. Jakob, B. C. Johnson, D. N. Jamieson, A. S. Dzurak, C. Ferrie, R. Blume-Kohout, and A. Morello, Precision tomography of a three-qubit donor quantum processor in silicon, Nature601, ...

2022

[3] [2]

X. Xue, M. Russ, N. Samkharadze, B. Undseth, A. Sam- mak, G. Scappucci, and L. M. K. Vandersypen, Quantum logic with spin qubits crossing the surface code threshold, Nature601, 343 (2022)

2022

[4] [3]

7.a-b,Path integral Monte Carlo simulations ofa)tunnel couplings andb)exchange couplings as a function of J-gate biasing in the model of FIG

A.Noiri, K.Takeda, T.Nakajima, T.Kobayashi, A.Sam- 10 P4 J14 P1 P4 P2 P3J34 J12 SET a -60 0 60 Position (nm) Electron Potential (eV) 0.0 0.5 1.0 1.5 -60 0 60 -0.1 -1.1 -0.6 -0.1 P2 P3 P1 P4 P1 P2 𝑽𝑽𝑱𝑱 (V) J12 J14 J34 J23 -1.1 -0.6 Electrostatic Simulations a Si SiO2 Path Integral Simulation of Tunnel and Exchange Rates P3 J14J34J12J23 Layer 1 Layer 3 Laye...

work page 2022

[5] [4]

A. R. Mills, C. R. Guinn, M. J. Gullans, A. J. Sigillito, M. M. Feldman, E. Nielsen, and J. R. Petta, Two-qubit silicon quantum processor with operation fidelity exceed- ing 99%, Science Advances8, eabn5130 (2022)

2022

[6] [5]

A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. H. Fong, S. D. Ha, D. R. Hulbert, C. A. C. Jack- son, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Universal logic with en- coded spin qubits in silic...

2023

[7] [7]

Petit, J

L. Petit, J. M. Boter, H. G. J. Eenink, G. Droulers, M. L. V. Tagliaferri, R. Li, D. P. Franke, K. J. Singh, J. S. Clarke, R. N. Schouten, V. V. Dobrovitski, L. M. K. Vandersypen, and M. Veldhorst, Spin lifetime and charge noise in hot silicon quantum dot qubits, Physical Review Letter121, 076801 (2018)

work page 2018

[8] [8]

C. H. Yang, R. C. C. Leon, J. C. C. Hwang, A. Saraiva, T. Tanttu, W. Huang, J. Camirand Lemyre, K. W. Chan, K. Y. Tan, F. E. Hudson, K. M. Itoh, A. Morello, M. Pioro-Ladrière, A. Laucht, and A. S. Dzurak, Oper- ation of a silicon quantum processor unit cell above one kelvin, Nature580, 350 (2020)

2020