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Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI

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arxiv 2411.14299 v5 pith:OCTFXKVT submitted 2024-11-21 cs.AR

Jitendra Bhandari , Vineet Bhat , Yuheng He , Hamed Rahmani , Siddharth Garg , Ramesh Karri This is my paper · ORCID
classification cs.AR
keywords netlistanalogcircuitgenerationllmsmasala-chaicircuitsspice
verification ladder T0 review T1 audit T2 compute T3 formal
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Masala-CHAI is a fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a long-standing challenge in circuit design automation: automating netlist generation for analog circuits. Automating this workflow could accelerate the creation of fine-tuned LLMs for analog circuit design and verification. In this work, we identify key challenges in automated netlist generation and evaluate multimodal capabilities of state-of-the-art LLMs, particularly GPT-4, in addressing them. We propose a three-step workflow to overcome existing limitations: labeling analog circuits, prompt tuning, and netlist verification. This approach enables end-to-end SPICE netlist generation from circuit schematic images, tackling the persistent challenge of accurate netlist generation. We utilize Masala-CHAI to collect a corpus of 7,500 schematics that span varying complexities in 10 textbooks and benchmark various open source and proprietary LLMs. Models fine-tuned on Masala-CHAI when used in LLM-agentic frameworks such as AnalogCoder achieve a notable 46% improvement in Pass@1 scores. We open-source our dataset and code for community-driven development.

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Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

    cs.AR 2026-07 conditional novelty 7.0 of 10

    An NDA-safe scrubbed boundary lets cloud LLMs optimize analog circuits in real Cadence flows; multi-model PVT benchmarks show successful closure on LC-VCO (7/11) and two-stage op-amp (4/11) tasks.

  2. OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning

    cs.CV 2026-03 conditional novelty 7.0 of 10

    OmniSch is the first benchmark exposing gaps in LMMs for PCB schematic visual grounding, topology-to-graph parsing, geometric weighting, and tool-augmented reasoning.

  3. AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation

    cs.CL 2025-06 conditional novelty 6.0 of 10

    Reinforcement learning with AI reward models improves an instruction-tuned LLM's analog power-converter topology generation, beating fine-tuning baselines and generalizing to 6-10 component circuits.

  4. DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining

    cs.LG 2025-02 conditional novelty 6.0 of 10

    A self-supervised graph encoder for device-level circuits improves prediction of circuit similarity, delays, and op-amp performance across analog and digital designs.

  5. Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation

    cs.SE 2026-07 conditional novelty 5.0 of 10

    ATLAS combines template-constrained LLM agents with Bayesian optimization to produce SAR ADC netlists that meet user specs in simulation.

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