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REVIEW 3 major objections 4 minor 28 references

Fabrication and characterization of InAs nanowire-based quantum dot structures utilizing buried bottom gates

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Buried polished TiN gates form quantum dots in InAs nanowires.

desk verdict A genuinely new fabrication route for flat buried gates that works, with a real but disclosable caveat about parasitic dots. read the letter →

arxiv 2411.19575 v1 pith:3BEQTTJS submitted 2024-11-29 cond-mat.mes-hall

Anton Faustmann , Patrick Liebisch , Benjamin Bennemann , Pujitha Perla , Mihail Ion Lepsa , Alexander Pawlis , Detlev Grützmacher , Joachim Knoch
show 1 more author
Thomas Schäpers
This is my paper · ORCID
classification cond-mat.mes-hall
keywords buriedbottomgatesTiNInAsnanowirequantumdotCoulombblockadesingle-electrontunnelingmechanicalpolishinggatefabrication
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that bottom gates for semiconductor nanowire quantum dots can be made by a planar buried-gate process: trenches etched into silicon are filled with sputtered TiN and mechanically polished flat, instead of being patterned by metal lift-off. If it works, this gives a smooth, scalable gate platform that avoids the roughness and dielectric charge traps typical of lift-off gates. As proof, the paper reports a gate pitch down to 60 nm, leakage below 1 nA at ±10 V at 4.2 K, and Coulomb diamonds in InAs nanowires placed on the gates, which it reads as single-electron tunneling through a gate-defined quantum dot.

What carries the argument

The key object is the buried bottom gate: a trench etched 120 nm deep into high-resistivity silicon, thermally oxidized to isolate adjacent lines, filled with sputtered TiN, and planarized by mechanical polishing with a SiO2 abrasive. The flatness of the resulting surface carries the argument because it removes the valleys and metal roughness that in lift-off gates create charge traps in the dielectric. To form a quantum dot, a triplet of these gates is used, with the two outer gates biased negative to create tunnel barriers and the middle gate acting as a plunger, and the device is read out in a two-terminal configuration through Coulomb diamond analysis.

What would settle it

Measure the same nanowire with the two outer barrier gates held at 0 V so no intended dot should form; if Coulomb diamonds still appear, the observed blockade is dominated by a parasitic dot rather than the buried gates, which would refute the central claim.

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Extended reading notes

Core claim

The central claim is that buried bottom gate electrodes, made by filling silicon trenches with sputtered TiN and planarizing with mechanical polishing, are a working alternative to lift-off bottom gates for defining quantum dots in InAs nanowires. The paper shows flat gate arrays in electron micrographs, measures leakage currents between neighboring gates, and presents differential-conductance stability diagrams. In the best device, clear Coulomb diamonds yield a charging energy around 1.5 meV and a plunger-gate lever arm around 0.009, with the interpretation that the dot forms between two negatively biased barrier gates under a plunger gate. Multiple gate triplets and a second device give charging energies of 1.5 to 2 meV, supporting the conclusion that buried gates reliably form quantum dots.

Load-bearing premise

The load-bearing premise is that the Coulomb diamonds come from a quantum dot deliberately formed between the two barrier gates, and not from a parasitic dot created by disorder, surface states, or trapped charge in the InAs nanowire.

Editorial extensions

If this is right

  • Gate pitch can be scaled to 60 nm and below, matching the spacing needed for dense nanowire qubit arrays.
  • Cryogenic gate leakage is low enough (around 1 nA at ±10 V) that gate operation is not limited by the insulator.
  • The flat surface removes a major source of dielectric charge traps, so gate hysteresis and charge noise should be smaller than for lift-off gates, though some hysteresis remains.
  • The process decouples gate metal choice from lift-off constraints, allowing sputtered superconductors such as TiN to be used directly.
  • The platform extends to gating two-dimensional materials and, with a doped substrate, to additional half-pitch gate sections.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A direct test of whether the observed dots are the intended barrier-defined dots would be to map how each gate's voltage shifts the Coulomb diamond edges and compare with a capacitive model; the paper's lever arms vary from 0.009 to 0.045, hinting that parasitic dots or gate crosstalk may contribute.
  • The measured hysteresis of about 0.08 V indicates trapped charge in the HfO2 layer, so a side-by-side noise comparison with lift-off gates would quantify the flat-surface advantage the authors expect.
  • The estimated induced superconducting gap (2Δ ≲ 0.15 meV) is far below bulk aluminum, suggesting the half-shell acts as a weak tunnel-coupled reservoir; this could be exploited for superconductor-mediated coupling of two dots, as the paper states as a future step.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper reports a buried bottom gate technology for semiconductor nanowire quantum dots: trenches etched into a Si substrate are filled with sputtered TiN and mechanically polished to a flat surface, achieving gate pitches down to 60 nm. The authors characterize the leakage between neighboring gates at room temperature and at 4.2 K, and present transport measurements on InAs nanowires placed on these gates, showing Coulomb blockade in gate sweeps and stability diagrams at temperatures of 60 and 600 mK. Charging energies around 1.5–2.1 meV and plunger gate lever arms between 0.008 and 0.05 are extracted. The manuscript claims that these results demonstrate the suitability of buried bottom gates for defining quantum dots in semiconductor nanowires.

Significance. If the central claim holds, this buried gate process is a valuable alternative to lift-off bottom gates for nanowire qubit devices, offering a flatter surface that may reduce charge noise and permit smaller gate pitches. The paper's concrete strengths are the detailed fabrication description, the leakage data that directly address a practical concern, and the clear Coulomb diamond features in Fig. 6 and the supplementary figures. However, the functionality claim is currently conditional: the manuscript does not establish that the observed quantum dots are the ones intentionally defined by the buried barrier gates, and the authors themselves raise the parasitic dot possibility in the supplementary material. The fabrication achievement is solid, but the proof-of-principle demonstration requires additional measurements or analysis to rule out dot formation by disorder or surface states.

major comments (3)
  1. [Formation of Quantum Dots in Nanowires / Supplementary Fig. S5] The central claim that the buried barrier gates define the observed quantum dot is not established. The only supporting statement is that "the contribution from the quantum dot is expected to be largely dominant" (Formation of Quantum Dots in Nanowires), but this is a plausibility argument rather than a measurement. The supplementary text for device D explicitly concedes that the plunger voltage below the barrier voltages "could suggest that the quantum dot observed here is actually not formed as intended by barrier gate electrodes." The manuscript contains no data showing the barrier gates independently controlling tunnel coupling, nor any measurement localizing the dot between the intended gates. A disorder-defined or surface-state-defined dot in the InAs nanowire would produce the same Coulomb diamond features. To support the proof-of-principle claim, please provide, for example, conductance traces as a function of barrier gate voltage, stability diagrams at several barrier gate settings, or a control experiment without intentional barriers, to demonstrate that the dot is tunable by the intended gates.
  2. [Fig. 6 and Table I] The stability diagram in Fig. 6 was "corrected for sudden jumps in the plunger gate potential by removing double features." Since the jumps are in the effective gate potential, removing them can alter the diamond slopes and hence the extracted lever arm α and charging energy EC. Please show the uncorrected data or provide a detailed, quantitative description of the correction procedure, including how many features were removed. In addition, the EC and α values in Table I are reported without error bars or a description of the fitting procedure, which is necessary given that the diamonds do not fully close due to the induced superconducting gap.
  3. [Formation of Quantum Dots in Nanowires, paragraph on EC and α] The text states that the induced superconducting gap (2Δ ≲ 0.15 meV) prevents the Coulomb diamonds from closing at charge degeneracy points. Because the lever arm is extracted from the diamond slopes VSD/ΔVPG, the finite gap introduces a systematic truncation that can bias the extracted slopes. The paper does not quantify this effect or describe how the open diamonds were used to determine α. Please provide an uncertainty estimate for the extracted parameters and explain how the finite gap was accounted for in the slope extraction.
minor comments (4)
  1. [Throughout] There are several typographical errors: "dieletric" in the Introduction, "mirco-scope" in the caption of Fig. 2, "strutures" in the Conclusion, and "the induced superconducting gap ... is manifests" in the Formation of Quantum Dots section. These should be corrected.
  2. [Fig. 5b] The hysteresis measurement is described qualitatively. For reproducibility, please specify the sweep rate and direction of the plunger gate voltage in the caption or text, since the magnitude of the observed offset (about 0.08 V) depends on these parameters.
  3. [Supplementary, Fig. S6] The caption states "charging energies around 1.7 − 1.9 mV"; the unit should be meV, consistent with the rest of the paper. Also check the main text for consistent use of "meV" versus "mV" when referring to EC.
  4. [Experimental, Quantum Dot Device Fabrication] The notation for the gate electrodes (I through VII) and the terms "barrier gates," "plunger gate," and "source-drain" would benefit from a brief definition, especially since the paper uses both Roman numerals and names (e.g., VBL and VBR) in the schematic and in the text.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the paper reports direct fabrication and transport measurements; extracted dot parameters are data-derived outputs, not fitted inputs used to generate the claims.

full rationale

The paper's central claims are experimental: buried TiN bottom gates with 60 nm pitch and low leakage were fabricated, and InAs nanowires on these gates showed Coulomb blockade. These are direct observations from SEM/FIB images, leakage traces, and stability diagrams; they do not depend on a derivation that presupposes the conclusion. The charging energies and lever arms in Table I are extracted from the slopes and sizes of measured Coulomb diamonds, not fitted parameters later relabeled as predictions. The plausibility statement that 'the contribution from the quantum dot is expected to be largely dominant' is an interpretive argument about two-terminal data, not a circular step. The supplementary material's device-D caveat that the low plunger voltage 'could suggest that the quantum dot observed here is actually not formed as intended by barrier gate electrodes' is an explicitly acknowledged limitation and a validity risk, but it is not circularity: a parasitic dot would still be a measured transport feature, and the fabrication claims do not reduce to the intended-dot assumption. Self-citations to Refs. [12] and [16] are used for background on InAs surface states and dielectric trapping, not as load-bearing uniqueness theorems or fitted constraints. No equation or parameter in the paper reduces to another by construction, and no prediction is claimed that is statistically forced from a fitted subset. Accordingly, the appropriate finding is no significant circularity, score 0.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The paper's central claim depends on interpretations rather than on fitted parameters or invented entities. The two main domain assumptions concern the origin of the measured transport features and the dominance of capacitive charging in the dot.

assumptions (3)
  • domain assumption Capacitive charging energy dominates over quantum confinement energies in the nanowire dot regime.
    Used to interpret the measured addition energy as Coulomb charging energy EC of 1.5 to 2 meV; invoked in the main text under 'Formation of Quantum Dots in Nanowires' and in the supplementary for device D.
  • domain assumption Transport is dominated by the gate-defined quantum dot, making two-terminal conductance measurements valid.
    Stated in the main text under 'Formation of Quantum Dots in Nanowires'; the paper relies on this to attribute Coulomb diamonds to the intended dot rather than to contact or parasitic barriers.
  • standard math The 2Delta/e enhancement of the Coulomb diamond bias window is caused by the induced superconducting gap from the Al half-shell.
    The paper uses this standard model for superconductor-semiconductor nanowires to estimate an upper bound 2Delta of about 0.15 meV (main text, stability diagram section).

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Cite this review

Pith. "Pith review of Fabrication and characterization of InAs nanowire-based quantum dot structures utilizing buried bottom gates." pith.science (2026). https://pith.science/paper/3BEQTTJS

@misc{pith2026241119575,
  author       = {Pith},
  title        = {Pith review of: Fabrication and characterization of InAs nanowire-based quantum dot structures utilizing buried bottom gates},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3BEQTTJS}},
  note         = {Machine review of arXiv:2411.19575}
}
read the original abstract

Semiconductor nanowires can be utilized to create quantum dot qubits. The formation of quantum dots is typically achieved by means of bottom gates created by a lift-off process. As an alternative, we fabricated flat buried bottom gate structures by filling etched trenches in a Si substrate with sputtered TiN, followed by mechanical polishing. This method achieved gate line pitches as small as 60 nm. The gate fingers have low gate leakage. As a proof of principle, we fabricated quantum dot devices using InAs nanowires placed on the gate fingers. These devices exhibit single electron tunneling and Coulomb blockade.

Figures

Figures reproduced from arXiv: 2411.19575 by the authors.

Figure 1
Figure 1. FIG. 1. a) Scanning electron micrograph of a buried bot [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. a) and b) Scanning electron micrograph of FIB cut [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. a) Scanning electron micrograph of device for [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: FIG. 4. a) and b) Leakage currents of two buried bot [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. a) Differential conductance through a nanowire [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

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Reference graph

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