Pith. sign in

REVIEW 4 major objections 6 minor 26 references

Design and Performance Analysis of an Ultra-Low Power Integrate-and-Fire Neuron Circuit Using Nanoscale Side-contacted Field Effect Diode Technology

T0 review · 4 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read This paper claims an S-FED-based integrate-and-fire neuron circuit that, in mixed-mode simulation, consumes 44 nW DC power and 0.964 fJ per spike while firing at 20 MHz, with a tunable threshold and less than 7% spike-amplitude variation…

desk verdict The device characterization is worth a look, but the headline power and energy numbers don't follow from the paper's own equations. read the letter →

arxiv 2412.12443 v1 pith:Q4MX6KJ2 submitted 2024-12-17 cs.AR

Seyedmohamadjavad Motaman , Sarah Sharif , Yaser Banad This is my paper · ORCID
classification cs.AR
keywords integrate-and-fireneuronside-contactedfield-effectdiodeneuromorphiccomputingultra-low-powercircuitspikingneuralnetworkPVTvariationenergyperspikeTCADsimulation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a neuron circuit built from nanoscale side-contacted field-effect diodes (S-FEDs) can beat published integrate-and-fire designs on power, per-spike energy, and spiking speed at the same time. In mixed-mode simulation, the circuit integrates synaptic current onto a 1 fF membrane capacitor, fires when the membrane voltage crosses a threshold set by gate-bias references, and resets through a diode-connected S-FED. The authors report 44 nW DC power, 0.964 fJ per spike, and a 20 MHz spiking frequency, and place those numbers below every row in their comparison table. They also show the firing threshold is tunable from 0.8 V to 1.4 V and that spike amplitude shifts by less than 7% across channel lengths of 7.5-15 nm, supply voltages of 0.8-1.2 V, and temperatures from -40°C to 120°C. If the claim holds, S-FEDs give neuromorphic designers a single-device replacement for the integration, conversion, reset, and buffering functions currently spread across multiple CMOS components.

What carries the argument

The load-bearing object is the Side-Contacted Field-Effect Diode (S-FED), a dual-gate device whose gate-source and gate-drain voltages jointly control a channel barrier, giving a high on/off current ratio and low parasitic capacitance. In the neuron, S-FED D1 acts as a tunable diode whose threshold is set by $V_{Ref1}$ and $V_{Ref2}$; D3 converts the integrated current into a voltage; D4 resets the spike node; D2 discharges the membrane capacitor after firing; and back-to-back inverters D5-D8 buffer and shape the output spike. The performance claims are computed from two accounting formulas: energy per spike $E_S = \frac{1}{T_{fs}}\int_0^T I_{synaptic}V_{membrane}\,dt$ and DC power $P = V_{dd}(I_{D5}+I_{D7})$. Threshold tunability comes from modulating the channel barrier of D1 with the two reference voltages, which changes how many synaptic input spikes must accumulate before the membrane potential reaches the firing point.

What would settle it

Add a current probe on the 1.2 V supply net in the same mixed-mode simulation, integrate $V_{dd}$ times the total supply current over one firing period, and compare with 0.964 fJ; a total-energy value that exceeds the paper's Eq. (1) result by more than the claimed 36% margin would falsify the central efficiency claim. Likewise, measuring total DC current instead of $I_{D5}+I_{D7}$ would either confirm or overturn the 44 nW figure.

Watch

Extended reading notes

Core claim

The central discovery, stated the way the authors would state it, is that the nanoscale S-FED is not just a low-power logic device but a complete integrate-and-fire neuron primitive. A dual-gate diode with a high on/off current ratio and low parasitic capacitance can serve as the tunable threshold element, the current-to-voltage converter, the reset switch, and the membrane-capacitor discharge switch in one circuit. Eight S-FEDs plus a 1 fF capacitor implement an IF neuron that, in TCAD mixed-mode simulation, consumes 44 nW from a 1.2 V supply, spends 0.964 fJ per spike, and fires at 20 MHz; the paper reports static power rising from 14 nW to 60 nW as channel length shrinks from 15 nm to 7.5 nm. The firing threshold moves from 0.8 V to 1.4 V as the gate reference voltages on the first S-FED are changed, and the number of input spikes needed to fire falls from ten to five as the input pulse width increases from 0.5 ns to 2 ns. These numbers are the paper's central evidence that S-FED-based neurons outperform existing simulated IF neurons.

Load-bearing premise

The load-bearing assumption is that the DC power of the neuron is fully given by $V_{dd}(I_{D5}+I_{D7})$ and the per-spike energy by $\frac{1}{T_{fs}}\int I_{synaptic}V_{membrane}dt$, so that the currents through the S-FEDs doing the actual integration, conversion, and reset can be ignored in the headline 44 nW and 0.964 fJ numbers.

Editorial extensions

If this is right

  • The reported 44 nW and 0.964 fJ per spike would place the S-FED neuron below the 1.5 fJ RRAM neuron and the 2.9 fJ FBFET neuron, making it the lowest simulated per-spike energy among the designs in the paper's comparison table.
  • The same circuit can change its firing threshold from 0.8 V to 1.4 V by adjusting only the gate reference voltages, so one neuron layout can implement different integration behaviors without redesign.
  • Less than 7% spike-amplitude variation across 7.5-15 nm channel length, 0.8-1.2 V supply, and -40°C to 120°C suggests the neuron can be used in dense arrays or harsh environments without per-neuron calibration.
  • 20 MHz spiking at 0.964 fJ per spike is faster than the 20 kHz FBFET comparator at comparable energy, so the design points toward real-time spike-processing applications.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's power formula counts only the inverter branch currents $I_{D5}+I_{D7}$; a fairer measure would include all eight S-FEDs and the membrane capacitor. Recomputing energy per spike from total supply current would be a direct test of the 44 nW and 0.964 fJ claims.
  • Since the S-FED is always ON for negative drain-source voltage (modes E-G), array-level designs must avoid reverse-bias conditions during reset or fan-out; the paper does not analyze this cascading constraint.
  • The tunable threshold could be exploited for dynamic gain control or homeostasis in a spiking network by modulating $V_{Ref1}$ and $V_{Ref2}$ in real time, but the paper only demonstrates static tuning.
  • All headline numbers come from mixed-mode TCAD simulation rather than fabricated hardware, so silicon measurement is the natural next test before treating this as a production neuromorphic element.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes an integrate-and-fire (IF) neuron circuit built from nanoscale side-contacted field-effect diodes (S-FEDs), simulated with Silvaco TCAD and mixed-mode circuit simulation. The authors report a power consumption of 44 nW, an energy per spike of 0.964 fJ, a spiking frequency of 20 MHz, threshold tunability from 0.8 V to 1.4 V, and PVT robustness with 'less than 7% spike amplitude variation' across channel length, supply, and temperature. The qualitative behavior — membrane integration, firing after a number of input spikes, reset, and threshold tunability — is demonstrated in transient waveforms. The quantitative claims, however, are derived from Eqs. (1) and (2), which do not define the quantities they are said to represent.

Significance. If the quantitative claims were correct, this would be a meaningful step toward energy-efficient neuromorphic hardware, as the reported energy per spike is lower than most prior simulated IF neurons. The paper has concrete strengths: it shows plausible integrate-and-fire dynamics in Figs. 4 and 7, demonstrates a tunable threshold mechanism in Figs. 5 and 6, and provides deterministic PVT sweeps in Figs. 8–10. The device-level simulation uses a standard TCAD toolchain with physical models. However, the headline numbers — and therefore the comparisons '85% lower power' and '36% energy improvement' — rest on equations whose units and current accounting are incorrect as written. The PVT claim is also not quantified consistently with the displayed supply-voltage dependence. Until the power and energy accounting is corrected and the PVT variation is reported numerically, the central contribution is not established. No code or calibrated compact model is provided, which limits reproducibility.

major comments (4)
  1. [Section III.C, Eq. (1)] Eq. (1) states E_S[J/spike] = (1/T_fs) ∫ I_synaptic V_membrane dt. The right-hand side has units of energy per unit time (average power), not energy per spike, since the integral of I·V is energy and the prefactor 1/T_fs divides by time. If T_fs is the firing period, the expression gives the average power drawn by the synaptic-input path over one period, not the per-spike energy. To obtain per-spike energy, the 1/T_fs prefactor should be removed and the integration window should include all current delivered during one integrate-and-fire cycle, including the five synaptic pulses in Fig. 4(a). As written, the reported 0.964 fJ/spike cannot be reproduced from Eq. (1), and the abstract's '36% improvement' claim is unsupported.
  2. [Section III.C, Eq. (2)] Eq. (2) defines total power consumption as Vdd(I_D5 + I_D7). This omits the supply current through D6 and D8 in the second back-to-back inverter, the currents through D1–D4 that carry integration, current-to-voltage conversion, and reset, the charge delivered to Cmem, and the power drawn by the reference-bias supplies VRef1, VRef2, VRef3, and VBG. The reported 44 nW is therefore not the total supply power of the neuron circuit. The authors should measure or calculate the current from every supply terminal and either report the total or provide a quantitative argument that the omitted paths are negligible. Without this, the '85% lower power' claim in the abstract is not supported.
  3. [Section IV, Figs. 8–10 and abstract] The abstract claims 'less than 7% spike amplitude variation' for channel length from 7.5 nm to 15 nm, supply voltage from 0.8 V to 1.2 V, and temperature from -40°C to 120°C. The paper never reports the numerical amplitude values or the percentage variation. Fig. 9(b) shows that the spike amplitude increases with supply voltage, and because Vdd defines the maximum spike level, the amplitude variation across a 0.8–1.2 V supply range is likely much larger than 7%. The threshold voltage is also shown to shift by about 200 mV across supply (Fig. 9(a)). Please plot or tabulate the actual spike amplitudes and compute the percentage variation separately for each variable; as written, the PVT robustness claim is not established and appears inconsistent with the displayed supply dependence.
  4. [Section IV, Fig. 8(d)] Fig. 8(d) shows static power varying from 14 nW to 60 nW as the channel length is swept from 15 nm to 7.5 nm — a factor of more than four. This is a wide range, and the paper does not state the nominal channel length or the conditions under which the headline 44 nW is obtained. The relationship between the 44 nW figure and the PVT power sweep needs to be made explicit. Without that, the reader cannot tell whether 44 nW is a best-case, nominal, or worst-case value, and the comparison in Table 2 is not meaningful.
minor comments (6)
  1. [References] References [10] and [13] both refer to Tuma et al. (2016), and references [11] and [14] both refer to Dutta et al. (2017). These duplicate citations should be consolidated.
  2. [Table 2] Table 2 is garbled: entries such as '11-×103' and '15-6.3×10' do not render as valid numeric values, and the power column is empty for most rows. Please reformat the table with clear units and correct numbers.
  3. [Section IV] The paragraph on temperature variation says 'As shown in Figure. 9(a-d)' when it should refer to Figure 10(a-d).
  4. [Abstract and Section III.C] The abstract contains the typo '0.9 64 fJ' with a stray space, and Eq. (1) uses both T and T_fs without defining the integration limits. Please define the integration window explicitly.
  5. [Section IV, Fig. 8] The text refers to 'Figure. 1(d)' when describing channel-length effects on static power; the correct reference is Figure 8(d).
  6. [Table 1 and Fig. 2] Mode H is used for D1 and is described in the text and Fig. 2(h), but Table 1 lists only modes A–G. Please add mode H to the table or describe its bias conditions explicitly.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity found: the reported performance metrics are simulation outputs from TCAD/mixed-mode analysis, not results fitted to or defined by the target claims.

full rationale

The quantitative claims (44 nW power, 0.964 fJ/spike, 20 MHz spiking frequency) are presented as simulation outputs from SILVACO TCAD and mixed-mode circuit simulation using stated physical models (BBT.KL, Conmob, Fldmob, SRH, Auger, bandgap narrowing, Lombardi CVT) and explicit bias, capacitance, and input-current parameters. There is no indication that any parameter was fitted to reproduce the reported power or energy figures, nor is any benchmark result renamed as an architectural contribution. The only self-citation ([27], the authors' prior MWSCAS paper) is used to state that the architecture was 'briefly introduced' earlier; the present paper's simulations and comparisons are self-contained, and [27] is not invoked as a uniqueness theorem or as evidence for the measured metrics. The energy and power definitions in Eqs. (1)-(2) are questionable on dimensional and completeness grounds (Eq. (1) as written has units of average power rather than energy per spike, and Eq. (2) omits the supply currents of D1-D4, D6, D8, and reference-bias circuitry), and the PVT robustness claim rests on deterministic single-point sweeps rather than statistical corners. These are correctness and validation weaknesses, not cases where a prediction reduces by construction to its own inputs. Accordingly, no circular step is established under the hard-evidence standard.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The central claims rest on the TCAD model being a faithful representation of the S-FED and on the energy/power definitions in Eqs. (1)-(2), both of which are assumed rather than demonstrated.

free parameters (4)
  • Membrane capacitance Cmem = 1 fF
    Hand-chosen value that sets the integration time constant and the energy scale; no design-space exploration or biological justification is given.
  • Synaptic input current amplitude = 250 nA
    Fixed input pulse amplitude; the number of pulses to fire and the Eq. (1) energy integral depend directly on it.
  • Gate reference biases VRef1/VRef2/VRef3 = 800/100/400 mV nominal
    Chosen biases set the threshold and the resistor-like behavior of D3; threshold tunability is achieved by changing these values.
  • Source/drain doping and gate work function = 1e21 cm^-3 and 4.7 eV
    Device-level simulation inputs selected by the authors; no sensitivity analysis or hardware calibration is provided.
assumptions (4)
  • domain assumption TCAD drift-diffusion models predict S-FED behavior accurately at 7.5-15 nm channel lengths.
    Section II uses BBT.KL, Conmob, Fldmob, SRH, Auger, bandgap narrowing, and Lombardi CVT models as ground truth; no measured silicon calibration is shown.
  • domain assumption Compact model extraction from TCAD preserves device behavior in mixed-mode simulation.
    Section III.D describes the extraction flow but quantifies no error introduced by the compact model.
  • ad hoc to paper S-FED mode H exists and behaves as a diode for D1.
    Section III.A biases D1 into mode H and cites Figure 2(h), but Table 1 defines only modes A-G, so the diode behavior is assumed without a table entry.
  • ad hoc to paper Eq. (1) gives the true energy per spike from the synaptic input path alone.
    The metric is defined by the authors and excludes reset, buffer, and discharge energy; dimensionally it resembles average power.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Design and Performance Analysis of an Ultra-Low Power Integrate-and-Fire Neuron Circuit Using Nanoscale Side-contacted Field Effect Diode Technology." pith.science (2026). https://pith.science/paper/Q4MX6KJ2

@misc{pith2026241212443,
  author       = {Pith},
  title        = {Pith review of: Design and Performance Analysis of an Ultra-Low Power Integrate-and-Fire Neuron Circuit Using Nanoscale Side-contacted Field Effect Diode Technology},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Q4MX6KJ2}},
  note         = {Machine review of arXiv:2412.12443}
}
read the original abstract

Enhancing power efficiency and performance in neuromorphic computing systems is critical for next-generation artificial intelligence applications. We propose the Nanoscale Side-contacted Field Effect Diode (S-FED), a novel solution that significantly lowers power usage and improves circuit speed, facilitating efficient neuron circuit design. Our innovative integrate-and-fire (IF) neuron model demonstrates exceptional performance metrics: 44 nW power consumption (85% lower than current designs), 0.964 fJ energy per spike (36% improvement over state-of-the-art), and 20 MHz spiking frequency. The architecture exhibits robust stability across process-voltage-temperature (PVT) variations, maintaining consistent performance with less than 7% spike amplitude variation for channel lengths from 7.5nm to 15nm, supply voltages from 0.8V to 1.2V, and temperatures from -40{\deg}C to 120{\deg}C. The model features tunable thresholds from 0.8V to 1.4V and reliable operation across input spike pulse widths from 0.5 ns to 2 ns. This significant advancement in neuromorphic hardware paves the way for more efficient brain-inspired computing systems.

Figures

Figures reproduced from arXiv: 2412.12443 by the authors.

Figure 3
Figure 3. After this analysis, we present mixed-mode simulation results for the circuit. We then demonstrate the threshold tunability of the IF neuron circuit and explore its operation under different pulse width variations of the input signal. Finally, we compare the performance of the nanoscale S-FED￾based IF neuron model with the latest state-of-the-art neuron models. FIGURE 2. I-V characteristics of S-FED in different ope… view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

26 extracted references · 23 canonical work pages

  1. [1]

    & Vlasov, Y

    Gokmen, T. & Vlasov, Y. Acceleration of deep neural network training with resistive cross -point devices: Design considerations. Front. Neurosci. 10, 333 (2016)

    work page 2016

  2. [2]

    W., Enkrich, C., Wegener, M

    Klein, M. W., Enkrich, C., Wegener, M. & Linden, S. Second - harmonic generation from magnetic metamaterials. Science 313, 502- 504 (2006)

    work page 2006

  3. [3]

    Kwon, D. et al. On -Chip training spiking neural networks using approximated backpropagation with analog synaptic devices. Front. Neurosci. 14, 423 (2020)

    work page 2020

  4. [4]

    & Salakhutdinov, R

    Srivastava, N., Hinton, G., Krizhevsky, A., Sutskever, I. & Salakhutdinov, R. Dropout: A simple way to prevent neural networks from overfitting. J. Mach. Learn. Res. 15, 1929 -1958 (2014).J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., v ol. 2. Oxford: Clarendon, 1892, pp.68–73

    work page 2014

  5. [5]

    Towards spike -based machine intelligence with neuromorphic computing,

    K. Roy, A. Jaiswal, and P. Panda, “Towards spike -based machine intelligence with neuromorphic computing,” Nature, vol. 575, no. 7784,pp. 607–617, Nov. 2019.K. Elissa, “Title of paper if known,” unpublished

    work page 2019

  6. [6]

    The SpiNNaker project,

    S. B. Furber, F. Galluppi, S. Temple, and L. A. Plana, “The SpiNNaker project,” Proc. IEEE, vol. 102, no. 5, pp. 652–665, May 2014

    work page 2014

  7. [7]

    Advancing neuromorphic computing with Loihi: A survey of results and outlook,

    M. Davies et al., “Advancing neuromorphic computing with Loihi: A survey of results and outlook,” Proc. IEEE, vol. 109, no. 5, pp. 911 – 934, May 2021

    work page 2021

  8. [8]

    Neuromorphic electronic systems,

    C. Mead, “Neuromorphic electronic systems,” Proc. IEEE, vol. 78, no. 10, pp. 1629–1636, Oct. 1990

    work page 1990

Show all 26 references
  1. [9]

    PCMO RRAM for integrate -and-fire neuron in spiking neural networks,

    S. Lashkare, S. Chouhan, T. Chavan, A. Bhat, P. Kumbhare, and U. Ganguly, “PCMO RRAM for integrate -and-fire neuron in spiking neural networks,” IEEE Electron Device Lett. , vol. 39, no. 4, pp. 484–487, Apr. 2018

    2018

  2. [11]

    Leaky integrate and fire neuron by charge -discharge dynamics in floating-body MOSFET,

    S. Dutta, V. Kumar, A. Shukla, N. R. Mohapatra, and U. Ganguly, “Leaky integrate and fire neuron by charge -discharge dynamics in floating-body MOSFET,” Sci. Rep., vol. 7, no. 1, p. 8257, Dec. 2017

    2017

  3. [12]

    A low-power adaptive integrate-and-fire neuron circuit,

    G. Indiveri, “A low-power adaptive integrate-and-fire neuron circuit,” in Proc. Int. Symp. Circuits Syst. (ISCAS) , vol. 4, Jun. 2003, p. 4, doi: 10.1109/ISCAS.2003.1206342

    2003 arXiv

  4. [13]

    Stochastic phase-change neurons,

    T. Tuma, A. Pantazi, M. Le Gallo, A. Sebastian, and E. Eleftheriou, “Stochastic phase-change neurons,” Nat. Nanotechnol., vol. 11, no. 8, pp. 693–699, Aug. 2016

    2016

  5. [14]

    Leaky integrate and fire neuron by charge-discharge dynamics in floating-body MOSFET,

    S. Dutta, V. Kumar, A. Shukla, N. R. Mohapatra, and U. Ganguly, “Leaky integrate and fire neuron by charge-discharge dynamics in floating-body MOSFET,” Sci. Rep., vol. 7, no. 1, p. 8257, Dec. 2017

    2017

  6. [15]

    A Split -Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit,

    K.-B. Choi et al., "A Split -Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit," Frontiers in neuroscience, vol. 12, p. 704, 2018, doi: 10.3389/fnins.2018.00704

    2018

  7. [16]

    & Kottantharayil, A

    Chatterjee, D. & Kottantharayil, A. A CMOS compatible bulk FinFET-based ultra low energy leaky integrate and fire neuron for spiking neural networks. IEEE Electron Device Lett. 40, 1301 –1304 (2019)

    2019

  8. [17]

    In IEEE Trans

    Chavan, Tanmay; Dutta, Sangya; Mohapatra, Nihar R.; Ganguly, Udayan (2020): Band -to-Band Tunneling Based Ultra -Energy- Efficient Silicon Neuron. In IEEE Trans. Electron Devices 67 (6), pp. 2614–2620. DOI: 10.1109/TED.2020.2985167

    2020

  9. [18]

    RRAM -Based Energy Efficient Scalable Integrate and Fire Neuron With Built -In Reset Circuit,

    A. Dongre and G. Trivedi, "RRAM -Based Energy Efficient Scalable Integrate and Fire Neuron With Built -In Reset Circuit," IEEE Trans. Circuits Syst. II , vol. 70, no. 3, pp. 909 –913, 2023, doi: 10.1109/TCSII.2022.3219203

    2023

  10. [19]

    Rasool, S

    Z. Rasool, S. Amin, D. Prasad, and N. Kumar, Implementation of Leaky Integrate and Fire neuron using Trench gate vertical FBFET (TG-V-FBFET) exploiting its Steep Subthreshold slope, 2024

    2024

  11. [20]

    Touchaee, B. J. & Manavizadeh, N. An inverter gate design based on nanoscale S-FED as a function of reservoir thickness. IEEE Trans. Electron Devices 62, 3147-3152 (2015)

    2015

  12. [21]

    Design and simulation of low - power logic gates based on nanoscale sidecontacted FED,

    B. J. Touchaei, N. Manavizadeh, “Design and simulation of low - power logic gates based on nanoscale sidecontacted FED,” IEEE Trans. Electron Devices, vol. 64, no. 1, pp. 306-311, 2017

    2017

  13. [22]

    Noise -Immune 6T SRAM Bit - Cells Based on Side-Contacted FED,

    T. Ghafouri and N. Manavizadeh, "Noise -Immune 6T SRAM Bit - Cells Based on Side-Contacted FED," IEEE Trans. Electron Devices, vol. 67, no. 12, pp. 5511 –5519, 2020, doi: 10.1109/TED.2020.3028342

    2020

  14. [23]

    Performance comparison of 6T SRAM bit-cells based on side -contacted FED and CMOS,

    T. Ghafouri and N. Manavizadeh, "Performance comparison of 6T SRAM bit-cells based on side -contacted FED and CMOS," Alexandria Engineering Journal, vol. 59, no. 5, pp. 3715–3729, 2020, doi: 10.1016/j.aej.2020.06.026

    2020 doi

  15. [24]

    Design and simulation of high - performance 2:1 multiplexer based on side -contacted FED,

    T. Ghafouri and N. Manavizadeh, "Design and simulation of high - performance 2:1 multiplexer based on side -contacted FED," Ain Shams Engineering Journal , vol. 12, no. 1, pp. 709 –716, 2021, doi: 10.1016/j.asej.2020.05.005

    2021 doi

  16. [25]

    ATLAS User’s Manual Device Simulation Software, Silvaco, Santa Clara, CA, USA https://www.eng.buffalo.edu › atlas_user_manual (2018)

    2018

  17. [26]

    Implementation and Characterization of an Integrate -and-Fire Neuron Circuit Using a Silicon Nanowire Feedback Field -Effect Transistor,

    Woo, S., Cho, J., Lim, D., Park, Y. -S., Cho, K., and Kim, S., “Implementation and Characterization of an Integrate -and-Fire Neuron Circuit Using a Silicon Nanowire Feedback Field -Effect Transistor,” IEEE Trans. Electron Devices, vol. 67, no. 7, pp. 2995 – 3000, 2020

    2020

  18. [27]

    Enhancing Neuromorphic Computing: A High-Speed, Low-Power Integrate-and- Fire Neuron Circuit Utilizing Nanoscale Side -Contacted Field Effect Diode Technology,

    S. Motaman, S. S. Sharifi, and Y. M. Banad, "Enhancing Neuromorphic Computing: A High-Speed, Low-Power Integrate-and- Fire Neuron Circuit Utilizing Nanoscale Side -Contacted Field Effect Diode Technology," in 2024 IEEE 67th International Midwest Symposium on Circuits and Syste...

    2024

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.