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Acc-SpMM: Accelerating General-purpose Sparse Matrix-Matrix Multiplication with GPU Tensor Cores

T0 review · 3 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read A new library claims general sparse matrix-matrix multiplication runs 2.52x faster than cuSPARSE on tensor cores.

desk verdict Solid tensor-core SpMM engineering with plausible speedups, but the swapped-operand MMA lacks a correctness proof or validation—fix that and this is a useful systems paper. read the letter →

arxiv 2501.09251 v1 pith:BQ3CUQNB submitted 2025-01-16 cs.DC

Haisha Zhao , San Li , Jiaheng Wang , Chunbao Zhou , Jue Wang , Zhikuang Xin , Shunde Li , Zhiqiang Liang
show 5 more authors
Zhijie Pan Fang Liu Yan Zeng Yangang Wang Xuebin Chi
This is my paper · ORCID
classification cs.DC
keywords SparseMatrix-MatrixMultiplicationTensorCoresGPUTF32LoadBalancingstorageformatDatareorderingPipelining
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that general-purpose sparse matrix-matrix multiplication (SpMM), a kernel at the heart of graph neural networks and scientific computing, can be made substantially faster on GPU tensor cores than current vendor and research kernels. The authors build Acc-SpMM, a library that combines four optimizations: a data-affinity reordering that packs nonzeros into denser tensor-core tiles, a compressed BitTCF format that encodes each tile's nonzero positions in a single 64-bit word, a double-buffered pipeline that overlaps sparse and dense loads with tensor-core MMA, and a sparsity-aware load balancer. On 414 benchmark matrices and 10 graph matrices, they report average speedups of 2.52x on RTX 4090, 1.91x on A800, and 1.58x on H100 over cuSPARSE, with higher peaks for matrices with long average row lengths. If these results hold, tensor cores become a practical target for general sparse workloads, not just structured or block-sparse ones.

What carries the argument

The central mechanism is the swapped-operand tensor-core MMA: instead of the usual TCMMA(fragA, fragB), the kernel calls TCMMA(fragB, fragA) after loading sparse tiles as 8x8 blocks and dense B as 8x16 fragments, so the sparse tile occupies the K dimension of the m16n8k8 instruction. This lets the kernel use 8x8 sparse tiles and a single uint64 bitmask per tile, improving tile density and enabling the BitTCF compression format. The rest of the machinery, namely data-affinity reordering, BitTCF compression, cp.async double buffering, and the load-balancing performance model with write-back cost, exists to feed that MMA with dense, local, prefetched data and to keep thread blocks equally busy.

What would settle it

Run Acc-SpMM on a small sparse matrix, such as a random 16x16 matrix with a known TF32 reference, and compare its output against an exact CPU or baseline reference; any tile-boundary mismatch in C would indicate that the swapped MMA layout is not equivalent. A second check is to instrument the register fragments before and after TCMMA(fragB, fragA) and confirm that the C fragment's row and column indexing matches the un-swapped m16n8k8 layout.

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Extended reading notes

Core claim

The central claim is that an SpMM kernel can extract tensor-core performance from general sparse matrices by treating the sparse operand as the right-hand factor in the warp-level MMA. After reordering the matrix so nonzeros cluster into 8x8 tiles, Acc-SpMM compresses each tile into a uint64 bitmask (BitTCF), loads dense tiles of B directly into registers, and issues TCMMA(fragB, fragA) with swapped operands so that each 8x8 sparse tile maps to the 8-wide K dimension of the m16n8k8 instruction. A double-buffer pipeline prefetches the next dense B tile, next sparse A tile, and next index array during the current MMA, and an adaptive load balancer redistributes TC blocks across thread blocks using a performance model that includes write-back time. The authors report that the combination yields 2.52x/1.91x/1.58x average speedups over cuSPARSE on RTX 4090/A800/H100, with peak speedups of 5.11x/4.68x/3.60x on matrices with large average row length.

Load-bearing premise

The load-bearing premise is that swapping the two operands inside the tensor-core matrix-multiply instruction, combined with the write-back remapping, computes exactly the same A times B result as the normal order; the paper motivates this with a citation to another kernel but gives no proof or diagram of the internal register layouts that would verify the switch.

Editorial extensions

If this is right

  • If the reported speedups are correct, SpMM no longer needs structured block sparsity to benefit from tensor cores; general matrices from GNNs and linear solvers can use them.
  • The BitTCF format shrinks per-nonzero position storage to a fixed 64-bit word per 8x8 tile, so memory footprint and format-conversion overhead both drop relative to the prior ME-TCF format.
  • The load-balancing model with write-back cost should make the kernel robust to the heavy-tailed row-length distributions common in real-world graph matrices.
  • On H100, where the baseline cuSPARSE kernel is strongest, Acc-SpMM still claims a 1.58x average advantage, suggesting the speedup is not just a weak baseline effect.
  • The pipeline and cache-policy choices are demonstrated for TF32, matching the precision most used in GNN workloads.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural testable extension is to apply the swapped-operand trick with larger MMA shapes, pairing the bitmask compression with bigger sparse tiles; density gains may grow with tile size if the fragment layouts permit it.
  • The paper explicitly leaves dense-matrix row reordering for future work; reordering the dense operand's rows to match the sparse column order should raise L1/L2 hit rates further, which is a direct consequence of their own cache-hit measurements.
  • Because the central claim is measured kernel time, reproducibility depends on the build environment, TF32 settings, and the exact baseline library version; an independent benchmark with reference-output checks would clarify how much of the gain comes from each of the four optimizations.
  • The correctness of the swapped MMA is asserted rather than proven, so a formal layout argument or a targeted microbenchmark on other tensor-core shapes would make the technique safer to adopt in other libraries.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes Acc-SpMM, a Tensor Core-based SpMM library for NVIDIA GPUs, and attributes its speedups to four techniques: a data-affinity reordering based on modularity, a bitmask compressed format called BitTCF, a double-buffered pipeline that overlaps global-memory loads with MMA operations, and an adaptive, sparsity-aware load balancer driven by a performance model. The central measured claim is an average speedup over cuSPARSE of 2.52x on RTX 4090, 1.91x on A800, and 1.58x on H100, with additional comparisons against DTC-SpMM, TCGNN, Sputnik, and SparseTIR on 10 representative matrices and 414 SuiteSparse matrices. The paper does not provide source code or an artifact, does not report run-to-run variance, and does not include any numerical correctness validation of the kernel.

Significance. If the measured speedups are correct and reproducible, this is a practically significant systems contribution: it demonstrates that general sparse matrices can be mapped to Tensor Cores with a combination of reordering, compression, pipelining, and load balancing, and it evaluates the approach across three current GPU architectures. The experimental breadth is a genuine strength, as is the fact that the comparison is against external baselines rather than fitted constants. However, the absence of a reproducibility artifact and, more importantly, the absence of any correctness check for the central kernel transformation prevent the results from being accepted as they stand.

major comments (3)
  1. [Section 4, Experimental methodology] The swapped-operand TCMMA call TCMMA(fragB, fragA, fragC) is the linchpin of the kernel, but the manuscript provides no proof, fragment-layout diagram, transpose identity, or numerical validation showing that this call computes the intended A x B result for the 8x8 sparse tiles and 8x16 dense tiles. The paper states only that the swap 'enables us to partition the sparse matrix A into 8x8 TC blocks' and cites reference [50], which is not sufficient. For the m16n8k8 MMA, the first operand has a 16x8 fragment shape and the second has an 8x8 fragment shape, so the pseudocode is dimensionally inconsistent unless fragB and fragA are transposed views and WTCREMAPPING (line 37) performs the corresponding inverse transpose. Because every speedup in Section 4.2 is an end-to-end kernel measurement, an incorrect fragment mapping would invalidate all reported results. The authors must either provide a rigorous layout-level derivation of the transpose identity, a diagram of the fragment layouts, and a numerical correctness test comparing Acc-SpMM's output against a reference SpMM implementation, or replace the operation with one whose correctness is transparent.
  2. [Section 3.5, Equation (4)] The experimental methodology is under-specified for the central claim. The paper says experiments use 'CUDA version 11.8 or higher' and compares against 'the widely used SpMM kernel in the cuSPARSE library,' but it does not state the cuSPARSE version, the specific API and internal algorithm selection, or whether the CUDA-core path or the Tensor Core path was used. It also does not report the number of runs or any variance/standard deviation. This matters because the headline H100 average speedup is 1.58x, and several per-matrix speedups are modest; without variance information the reader cannot judge whether differences are stable. I recommend that the authors provide a full configuration table, repetition counts, variance bars or distributions, and, ideally, an artifact or source-code release so that the measured claims can be reproduced.
  3. [Section 3.3] The adaptive load-balancing contribution is evaluated only through end-to-end throughput comparisons; the performance model itself is not validated. Equation (4) uses theoretical peak bandwidth and FLOPS and ignores cache effects, memory latency, and the cost of the reordered/compressed format, yet it is used to redistribute TC blocks. The thresholds (IBD greater than 8, maximum 32 TC blocks per TB) are introduced without sensitivity analysis. Since load balancing is one of the four claimed contributions, the authors should validate the model's predicted per-TB times against measurements and show that the results are not sensitive to the two ad-hoc thresholds.
minor comments (5)
  1. [Section 3.3] The comment 'Prefetch ATile and AToBTile to SHEM' contains a typo: 'SHEM' should be 'SHM' (shared memory).
  2. [Section 4.1] The text refers to both TCLocalBit and TCLocalId when describing the compressed format; the relationship between these two names should be clarified, and the figure should use the same notation.
  3. [Section 4.3.1] The abbreviation AvgL is used throughout the evaluation but is defined only in the table caption ('average nnz length in each row of dataset'); it should be defined in the text before first use.
  4. [Section 4.3.2] The cache hit rate measurements are reported as absolute values and improvements, but the methodology (e.g., profiling counters, kernel configuration, whether hit rates are measured for the whole kernel or per phase) is not described.
  5. [Section 4.3.2] The compression ratio comparison in Figure 12 is not precisely defined; the authors should state whether it is bytes of the sparse format relative to TCF, CSR, or ME-TCF, and whether the dense B and C matrices are excluded.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the claimed speedups are empirical comparisons against external baselines, and no load-bearing result is reduced to a fitted parameter or self-citation.

full rationale

Acc-SpMM's central claims are measured end-to-end performance numbers against cuSPARSE, DTC-SpMM, TCGNN-SpMM, SparseTIR, and Sputnik on real GPU hardware. These are external empirical benchmarks, not derivations from fitted constants. The performance model in Equation (4) uses theoretical memory bandwidth and theoretical TF32 FLOPS to distribute TC blocks among thread blocks; it does not predict the headline speedups and is not fit to them. The load-balancing thresholds (IBD > 8, 32 TC blocks per TB) are hand-chosen engineering parameters, not outputs claimed as predictions. No self-citation is load-bearing: the swapped-operand MMA idea is attributed to prior work FlashSparse [50], and DTC-SpMM [24] is an external baseline, not an author self-citation. The paper also reports cases where its optimizations reduce performance (e.g., protein and FY-RSR after reordering), which is inconsistent with retrofitting a claim to predetermined outcomes. The unresolved question about whether the swapped TCMMA operand order correctly computes A x B is a correctness/validation gap, but it is not circularity: the paper does not assume that correctness as an input to any derivation. Overall, the derivation chain is self-contained with respect to the measured results, so the circularity score is 0.

Assumptions & free parameters 3 free parameters · 4 assumptions · 1 invented entities

The central claims rest on a standard modularity-based graph reordering framework, an untested instruction-layout assumption for swapped MMA, a simplified performance model used for load balancing, and hand-set thresholds. The main new construct is the BitTCF data structure; no new physical entities are proposed.

free parameters (3)
  • IBD threshold = 8
    Hand-set threshold in Section 3.5 deciding when to apply load balancing; no sensitivity analysis or selection criterion is given.
  • Max TC blocks per TB = 32
    Hand-set cap in Section 3.5 for load redistribution; no derivation or sensitivity study is provided.
  • TC block tile size = 8x8
    Design choice in Section 3.3 to fit the uint64 bitmask and the m16n8k8 MMA shape; affects density and format size.
assumptions (4)
  • ad hoc to paper The swapped MMA operand order TCMMA(fragB, fragA) produces the correct C result for the 8x8 and 8x16 tile layouts.
    Algorithm 2 lines 28 and 35 use the swapped order, but the paper does not prove or document the fragment-layout equivalence.
  • domain assumption Storing original column indices in SparseAToB makes row reordering of the dense matrix B unnecessary.
    Section 3.3 introduces SparseAToB for this purpose, but the correctness of the remapping is not formally verified.
  • ad hoc to paper The performance model in Equation (4) with theoretical bandwidth and FLOPS adequately estimates per-thread-block execution time.
    Section 3.5 uses this model to redistribute TC blocks; it ignores latency, occupancy, synchronization, and cache effects.
  • domain assumption The 414 SuiteSparse matrices and 10 representative matrices are representative of general-purpose SpMM workloads.
    Section 4.1 selects datasets following DTC-SpMM, but no justification is given that these cover the full distribution of real SpMM inputs.
invented entities (1)
  • BitTCF compressed format
    purpose: Stores the positions of nonzeros in each 8x8 TC block as a single uint64 bitmask to reduce memory footprint and decompression overhead.
    Introduced in Section 3.3. Its effectiveness is measured in Section 4.3.2, but no code or artifact is released, so the claims can only be verified by reimplementation.

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Cite this review

Pith. "Pith review of Acc-SpMM: Accelerating General-purpose Sparse Matrix-Matrix Multiplication with GPU Tensor Cores." pith.science (2026). https://pith.science/paper/BQ3CUQNB

@misc{pith2026250109251,
  author       = {Pith},
  title        = {Pith review of: Acc-SpMM: Accelerating General-purpose Sparse Matrix-Matrix Multiplication with GPU Tensor Cores},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BQ3CUQNB}},
  note         = {Machine review of arXiv:2501.09251}
}
read the original abstract

General-purpose Sparse Matrix-Matrix Multiplication (SpMM) is a fundamental kernel in scientific computing and deep learning. The emergence of new matrix computation units such as Tensor Cores (TCs) brings more opportunities for SpMM acceleration. However, in order to fully unleash the power of hardware performance, systematic optimization is required. In this paper, we propose Acc-SpMM, a high-performance SpMM library on TCs, with multiple optimizations, including data-affinity-based reordering, memory efficient compressed format, high-throughput pipeline, and adaptive sparsity-aware load balancing. In contrast to the state-of-the-art SpMM kernels on various NVIDIA GPU architectures with a diverse range of benchmark matrices, Acc-SpMM achieves significant performance improvements, on average 2.52x (up to 5.11x) speedup on RTX 4090, on average 1.91x (up to 4.68x) speedup on A800, and on average 1.58x (up to 3.60x) speedup on H100 over cuSPARSE.

Figures

Figures reproduced from arXiv: 2501.09251 by the authors.

Figure 1
Figure 1. The overview of Acc-SpMM Acc-SpMM consists of four key components, as shown in [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. The design of BitTCF format. The size of𝑇𝐶𝐿𝑜𝑐𝑎𝑙𝐼𝑑 in ME-TCF corresponds to the num￾ber of nnzs, representing original positions of each nnz. 𝑇𝐶𝐿𝑜𝑐𝑎𝑙𝐼𝑑 stores all the positions of nnzs in each TC block with a int8, and in a 8 × 8 tile of TC block, there are at least 8 nnzs and at most 64 nnzs, which will cost at least 64 bit and at most 512 bit to store the position of each nnz in a TC block with ME-TCF format. We de… view at source ↗
Figure 4
Figure 4. The data movement of Acc-SpMM. TC block is moved to shared memory for reuse. Dense 𝐵 tile is moved directly to registers. Dense matrix 𝐶 is moved to global mem￾ory from registers. Least bubble double-buffers pipeline. To reduce pipeline bubbles, we propose a high-throughput pipeline, as shown in [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Comparisons between our proposed pipeline(b) with DTC-pipeline(a). GToReg: global memory to register; GToSHM: global memory to shared memory; TCMMA: ten￾sor core mma. 3.5 Adaptive sparsity-aware load balancing Due to the various sparsity of different sparse matrices, t…
Figure 6
Figure 6. Figure 6: The diagram of adaptive sparsity-aware load bal￾ancing. (a) is without load balancing; (b) is with load balanc￾ing. We define a metric, 𝐼𝐵𝐷, as shown in Equation (3), to measure the degree of imbalance in the sparse matrix, where 𝑇𝐶𝑏𝑙𝑜𝑐𝑘𝑃𝑒𝑟𝑅𝑜𝑤𝑊 𝑖𝑛𝑑𝑜𝑤 represents the num…
Figure 8
Figure 8. Figure 8: The performance of normalized speedup and de￾tailed Gflops on A800. In [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 7
Figure 7. Figure 7: The performance of normalized speedup and de￾tailed Gflops on RTX4090. On various NVIDIA GPU architectures, our proposed Acc￾SpMM has always maintained good performance. Notably, on H100, where the performance of cuSPARSE-SpMM has been greatly improved, Acc-SpMM still …
Figure 9
Figure 9. Figure 9: The performance of normalized speedup and de￾tailed Gflops on H100. 4.3 Detailed evaluation 4.3.1 Evaluation of data-affinity based reordering. Com￾pared to state-of-the-art reordering algorithms, our pro￾posed reordering algorithm significantly improves data den￾sity …
Figure 11
Figure 11. Figure 11: (a) demonstrates significant improvements in L1 cache hit rate across most datasets, with a peak increase of 17.56%. Similarly, as depicted in [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 10
Figure 10. Figure 10: Comparisons on MeanNNZTC with different reordering method. Compared to DTC-LSH and Rabbit Order, our algorithm efficiently improves the MeanNNZTC across all 10 matrices as well as the 414 matrices from the SuiteSparse Collection, with average gains of 1.28× and 1.10×,…
Figure 12
Figure 12. Figure 12: Comparisons of compression ratio among CSR, ME-TCF and BitTCF based on TCF [38]. nnzs. ME-TCF further compresses the reordered matrix by using int8 to store the relative position of each nnz. Building on the reordered matrix, BitTCF utilizes a fixed uint64 to store th…
Figure 14
Figure 14. Figure 14: Comparisons of compute throughput and mem￾ory throughput between with load balance and without load balance on A800 (a) and H100 (b). 4.3.5 The ablation experiments. To evaluate the effec￾tiveness of different optimization techniques on the overall performance of Acc-…
Figure 13
Figure 13. Figure 13: Comparisons of speedup and GFLOPS between DTC-pipeline and Acc-pipeline on A800. 4.3.4 Evaluation of adaptive load-balancing [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 15
Figure 15. Figure 15: The ablation study on H100 with a feature dim of 128. Base: DTC-SpMM method without load balancing; BTCF: BitTCF; RO: Data-affinity reordering; CP: Cache policy control; PP: Pipeline; LB: Load balancing. 5 Related Work Given an m-by-k sparse matrix 𝐴 and a k-by-n dens…

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Reference graph

Works this paper leans on

59 extracted references · 56 canonical work pages · cited by 1 Pith paper

  1. [50]

    FlashSparse: Minimizing Computation Redundancy for Fast Sparse Matrix Multiplications on Tensor Cores

    Jinliang Shi, Shigang Li, Youxuan Xu, Rongtian Fu, Xueying Wang, and Tong Wu. Flashsparse: Minimizing computation redundancy for fast sparse matrix multiplications on tensor cores. arXiv preprint arXiv:2412.11007, 2024

    work page Pith review arXiv 2024

  2. [1]

    Garzón, and J

    Francisco Vázquez, Ester M. Garzón, and J. J. Fernández. A matrix approach to tomographic reconstruction and its implementation on gpus. Journal of structural biology , 170 1:146–51, 2010

    work page 2010

  3. [2]

    Optimizing sparse matrix-multiple vectors multiplication for nuclear configuration interaction calculations

    Hasan Metin Aktulga, Aydın Buluç, Samuel Williams, and Chao Yang. Optimizing sparse matrix-multiple vectors multiplication for nuclear configuration interaction calculations. 2014 IEEE 28th International Parallel and Distributed Processing Symposium , pages 1213–1222, 2014. 11

    work page 2014

  4. [3]

    Bader, Aydın Buluç, Franz Franchetti, John R

    Jeremy Kepner, Peter Aaltonen, David A. Bader, Aydın Buluç, Franz Franchetti, John R. Gilbert, Dylan Hutchison, Manoj Kumar, An- drew Lumsdaine, Henning Meyerhenke, Scott McMillan, Carl Yang, John Douglas Owens, Marcin Zalewski, Timothy G. Mattson, and José E. Moreira. Mathematical foundations of the graphblas. 2016 IEEE High Performance Extreme Computing...

    work page 2016

  5. [4]

    Dongarra, Axel Ruhe, Henk A

    James Demmel, Jack J. Dongarra, Axel Ruhe, Henk A. van der Vorst, and Zhaojun Bai. Templates for the solution of algebraic eigenvalue problems. In Software, environments, tools, 2000

    work page 2000

  6. [5]

    A high- performance parallel algorithm for nonnegative matrix factorization

    Ramakrishnan Kannan, Grey Ballard, and Haesun Park. A high- performance parallel algorithm for nonnegative matrix factorization. Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming , 2015

    work page 2015

  7. [6]

    Gordon E. Moon, J. Austin Ellis, Aravind Sukumaran-Rajam, Srinivasan Parthasarathy, and P. Sadayappan. Alo-nmf: Accelerated locality- optimized non-negative matrix factorization. Proceedings of the 26th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining, 2020

    work page 2020

  8. [7]

    Explor- ing data layout for sparse tensor times dense matrix on gpus

    Khalid Ahmad, Cris Cecka, Michael Garland, and Mary Hall. Explor- ing data layout for sparse tensor times dense matrix on gpus. ACM Transactions on Architecture and Code Optimization , 21:1 – 20, 2023

    work page 2023

Show all 59 references
  1. [8]

    Google’s pagerank and beyond: The science of search engine rankings, 2006

    Amy N Langville. Google’s pagerank and beyond: The science of search engine rankings, 2006

    2006

  2. [9]

    Multi- scale spectral decomposition of massive graphs

    Si Si, Donghyuk Shin, Inderjit S Dhillon, and Beresford N Parlett. Multi- scale spectral decomposition of massive graphs. Advances in Neural Information Processing Systems, 27, 2014

    2014

  3. [10]

    Graphblast: A high-performance linear algebra-based graph framework on the gpu

    Carl Yang, Aydın Buluç, and John Douglas Owens. Graphblast: A high-performance linear algebra-based graph framework on the gpu. ACM Transactions on Mathematical Software (TOMS) , 48:1 – 51, 2019

    2019

  4. [11]

    Advances in knowledge discovery and data mining

    Honghua Dai, Ramakrishnan Srikant, and Chengqi Zhang. Advances in knowledge discovery and data mining. In Lecture Notes in Computer Science, 2004

    2004

  5. [12]

    Maxk-gnn: Extremely fast gpu kernel design for accelerating graph neural networks training

    Hongwu Peng, Xi Xie, Kaustubh Shivdikar, Md Amit Hasan, Jiahui Zhao, Shaoyi Huang, Omer Khan, David Kaeli, and Caiwen Ding. Maxk-gnn: Extremely fast gpu kernel design for accelerating graph neural networks training. Proceedings of the 29th ACM International Conference on Archi...

    2023

  6. [13]

    Algorithm/hardware co-optimization for sparsity-aware spmm acceleration of gnns

    Yingxue Gao, Lei Gong, Chao Wang, Teng Wang, Xi Li, and Xuehai Zhou. Algorithm/hardware co-optimization for sparsity-aware spmm acceleration of gnns. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 42:4763–4776, 2023

    2023

  7. [14]

    Dgi: An easy and efficient framework for gnn model evaluation

    Peiqi Yin, Xiao Yan, Jinjing Zhou, Qiang Fu, Zhenkun Cai, James Cheng, Bo Tang, and Minjie Wang. Dgi: An easy and efficient framework for gnn model evaluation. Proceedings of the 29th ACM SIGKDD Conference on Knowledge Discovery and Data Mining , 2023

    2023

  8. [15]

    isplib: A library for accelerating graph neural networks using auto- tuned sparse operations

    Md Saidul Hoque Anik, Pranav Badhe, Rohit Gampa, and Ariful Azad. isplib: A library for accelerating graph neural networks using auto- tuned sparse operations. Companion Proceedings of the ACM on Web Conference 2024, 2024

    2024

  9. [16]

    Language models are few-shot learners

    Tom Brown, Benjamin Mann, Nick Ryder, Melanie Subbiah, Jared D Kaplan, Prafulla Dhariwal, Arvind Neelakantan, Pranav Shyam, Girish Sastry, Amanda Askell, Sandhini Agarwal, Ariel Herbert-Voss, Gretchen Krueger, Tom Henighan, Rewon Child, Aditya Ramesh, Daniel Ziegler, Jeffrey W...

    1901

  10. [17]

    Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks

    Torsten Hoefler, Dan Alistarh, Tal Ben-Nun, Nikoli Dryden, and Alexandra Peste. Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks. J. Mach. Learn. Res., 22:241:1–241:124, 2021

    2021

  11. [18]

    Generating long sequences with sparse transformers

    Rewon Child, Scott Gray, Alec Radford, and Ilya Sutskever. Generating long sequences with sparse transformers. ArXiv, abs/1904.10509, 2019

    1904 arXiv

  12. [19]

    Heuristic adaptability to input dynamics for spmm on gpus

    Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, and Yu Wang. Heuristic adaptability to input dynamics for spmm on gpus. Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022

    2022

  13. [20]

    Zaharia, Cliff Young, and Erich Elsen

    Trevor Gale, Matei A. Zaharia, Cliff Young, and Erich Elsen. Sparse gpu kernels for deep learning. SC20: International Conference for High Performance Computing, Networking, Storage and Analysis , pages 1–14, 2020

    2020

  14. [21]

    Sadayappan

    Changwan Hong, Aravind Sukumaran-Rajam, Israt Nisa, Kunal Singh, and P. Sadayappan. Adaptive sparse tiling for sparse matrix multipli- cation. Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming, 2019

    2019

  15. [22]

    Ge- spmm: General-purpose sparse matrix-matrix multiplication on gpus for graph neural networks

    Guyue Huang, Guohao Dai, Yu Wang, and Huazhong Yang. Ge- spmm: General-purpose sparse matrix-matrix multiplication on gpus for graph neural networks. SC20: International Conference for High Performance Computing, Networking, Storage and Analysis , pages 1–12, 2020

    2020

  16. [23]

    A novel data transformation and execution strategy for accelerating sparse ma- trix multiplication on gpus

    Peng Jiang, Changwan Hong, and Gagan Agrawal. A novel data transformation and execution strategy for accelerating sparse ma- trix multiplication on gpus. Proceedings of the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming , 2020

    2020

  17. [24]

    Dtc-spmm: Bridging the gap in accelerating general sparse matrix multiplication with tensor cores

    Ruibo Fan, Wei Wang, and Xiao-Xia Chu. Dtc-spmm: Bridging the gap in accelerating general sparse matrix multiplication with tensor cores. Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3 , 2024

    2024

  18. [25]

    Efficient quantized sparse matrix operations on tensor cores

    Shigang Li, Kazuki Osawa, and Torsten Hoefler. Efficient quantized sparse matrix operations on tensor cores. SC22: International Confer- ence for High Performance Computing, Networking, Storage and Analysis, pages 1–15, 2022

    2022

  19. [26]

    Ef- ficient tensor core-based gpu kernels for structured sparsity under reduced precision

    Zhaodong Chen, Zheng Qu, Liu Liu, Yufei Ding, and Yuan Xie. Ef- ficient tensor core-based gpu kernels for structured sparsity under reduced precision. SC21: International Conference for High Performance Computing, Networking, Storage and Analysis , pages 1–13, 2021

    2021

  20. [27]

    Castro, Diego Andrade, and Basilio B

    Roberto L. Castro, Diego Andrade, and Basilio B. Fraguela. Probing the efficacy of hardware-aware weight pruning to optimize the spmm routine on ampere gpus. Proceedings of the International Conference on Parallel Architectures and Compilation Techniques , 2022

    2022

  21. [28]

    Gloria Ortega López, Francisco Vázquez, Inmaculada García, and Es- ter M. Garzón. Fastspmm: An efficient library for sparse matrix matrix product on gpus. Comput. J., 57:968–979, 2014

    2014

  22. [29]

    Accelerating matrix multiplication with block sparsity

    NVIDIA. Accelerating matrix multiplication with block sparsity. Tech- nical Report, 2021

    2021

  23. [30]

    Dongarra

    Hartwig Anzt, Stanimire Tomov, and Jack J. Dongarra. Accelerating the lobpcg method on gpus using a blocked sparse matrix vector product. In Spring Simulation Multiconference, 2015

    2015

  24. [31]

    Regularizing irregularity: bitmap- based and portable sparse matrix multiplication for graph data on gpus

    Jianting Zhang and Le Gruenwald. Regularizing irregularity: bitmap- based and portable sparse matrix multiplication for graph data on gpus. Proceedings of the 1st ACM SIGMOD Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data A...

    2018

  25. [32]

    Rabbit order: Just-in-time parallel reordering for fast graph analysis

    Junya Arai, Hiroaki Shiokawa, Takeshi Yamamuro, Makoto Onizuka, and Sotetsu Iwamura. Rabbit order: Just-in-time parallel reordering for fast graph analysis. 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pages 22–31, 2016

    2016

  26. [33]

    Sadayappan

    Süreyya Emre Kurt, Aravind Sukumaran-Rajam, Fabrice Rastello, and P. Sadayappan. Efficient tiled sparse matrix multiplication through matrix signatures. SC20: International Conference for High Performance Computing, Networking, Storage and Analysis , pages 1–14, 2020. 12

    2020

  27. [34]

    Demystifying tensor cores to optimize half-precision matrix multiply

    Da Yan, Wei Wang, and Xiaowen Chu. Demystifying tensor cores to optimize half-precision matrix multiply. 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) , pages 634–643, 2020

    2020

  28. [35]

    Neal Clayton Crago, Sana Damani, Karthikeyan Sankaralingam, and Stephen W. Keckler. Wasp: Exploiting gpu pipeline parallelism with hardware-accelerated automatic warp specialization. 2024 IEEE In- ternational Symposium on High-Performance Computer Architecture (HPCA), pages 1–16, 2024

    2024

  29. [36]

    Stephenson, and Stephen W

    Neal Clayton Crago, Mark W. Stephenson, and Stephen W. Keckler. Exposing memory access patterns to improve instruction and mem- ory efficiency in gpus. ACM Transactions on Architecture and Code Optimization (TACO), 15:1 – 23, 2018

    2018

  30. [37]

    Davis and Yifan Hu

    Timothy A. Davis and Yifan Hu. The university of florida sparse matrix collection. ACM Trans. Math. Softw., 38:1:1–1:25, 2011

    2011

  31. [38]

    In 2023 USENIX Annual Technical Conference (USENIX ATC 23), pages 149–164, 2023

    Yuke Wang, Boyuan Feng, Zheng Wang, Guyue Huang, and Yufei Ding.{TC-GNN}: Bridging sparse{GNN} computation and dense tensor cores on{GPUs}. In 2023 USENIX Annual Technical Conference (USENIX ATC 23), pages 149–164, 2023

    2023

  32. [39]

    Sparse- tir: Composable abstractions for sparse compilation in deep learning

    Zihao Ye, Ruihang Lai, Junru Shao, Tianqi Chen, and Luis Ceze. Sparse- tir: Composable abstractions for sparse compilation in deep learning. Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3 , 2022

    2022

  33. [40]

    Chien, Philippe Vandermersch, and Ujval Kapasi

    Maxim Naumov, L. Chien, Philippe Vandermersch, and Ujval Kapasi. Cusparse library. In GPU Technology Conference, 2010

    2010

  34. [41]

    https://developer.nvidia.com/rtx-4090- graphics-cards

    Nvidia rtx 4090 architecture. https://developer.nvidia.com/rtx-4090- graphics-cards. Accessed: 2023-04-01

    2023

  35. [42]

    Nvidia a100: A 16-trump tensor core gpu architecture.Journal of Supercomputing, 56(2):1–1, 2020

    NVIDIA. Nvidia a100: A 16-trump tensor core gpu architecture.Journal of Supercomputing, 56(2):1–1, 2020

    2020

  36. [43]

    https://developer.nvidia

    Nvidia h100 tensor core gpu architecture. https://developer.nvidia. com/h100-technology-deep-dive , 2020

    2020

  37. [44]

    https://developer.nvidia.com/cuda-toolkit

    CUDA Toolkit - Free Tools and Training — developer.nvidia.com. https://developer.nvidia.com/cuda-toolkit. [Accessed 12-01-2025]

    2025

  38. [45]

    The Volta Architecture Whitepaper

    NVIDIA. The Volta Architecture Whitepaper. 2018. [Online; accessed 1st. April 2023]

    2018

  39. [46]

    NVIDIA. PTX ISA. NVIDIA Corporation, USA, 2024. [Online; accessed 1st June 2024]

    2024

  40. [47]

    Iterative Methods for Sparse Linear Systems

    Youcef Saad. Iterative Methods for Sparse Linear Systems . SIAM, 2003

    2003

  41. [48]

    Barrett, M

    R. Barrett, M. Berry, T. F. Chan, J. Demmel, J. Donato, J. Dongarra, V. Eijkhout, R. Pozo, C. Romine, and H. Van der Vorst.Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods, 2nd Edition. SIAM, Philadelphia, PA, 1994

    1994

  42. [49]

    Finding and evaluating community structurein networks

    Mark EJ Newman. Finding and evaluating community structurein networks. Physical review E, 69(26113):1–16, 2004

    2004

  43. [51]

    Snap: A general-purpose network analy- sis and graph-mining library

    Jure Leskovec and Rok Sosič. Snap: A general-purpose network analy- sis and graph-mining library. ACM Transactions on Intelligent Systems and Technology (TIST), 8(1):1–20, 2016

    2016

  44. [52]

    Deep graph library: towards efficient and scalable deep learning on graphs

    Minjie Wang, Lingfan Yu, Quan Gan Da Zheng, Yu Gai, Zihao Ye, Mufei Li, Jinjing Zhou, Qi Huang, Chao Ma, Ziyue Huang, et al. Deep graph library: towards efficient and scalable deep learning on graphs. corr abs/1909.01315 (2019). arXiv preprint arXiv:1909.01315, 2019

    2019 arXiv

  45. [53]

    Open graph benchmark: Datasets for machine learning on graphs

    Weihua Hu, Matthias Fey, Marinka Zitnik, Yuxiao Dong, Hongyu Ren, Bowen Liu, Michele Catasta, and Jure Leskovec. Open graph benchmark: Datasets for machine learning on graphs. Advances in neural information processing systems , 33:22118–22133, 2020

    2020

  46. [54]

    A software package for partitioning unstructured graphs, partitioning meshes, and computing fill-reducing orderings of sparse matrices

    George Karypis and Vipin Kumar. A software package for partitioning unstructured graphs, partitioning meshes, and computing fill-reducing orderings of sparse matrices. University of Minnesota, Department of Computer Science and Engineering, Army HPC Research Center, Min- neapo...

    1998

  47. [55]

    Xinyu Que, Fabio Checconi, Fabrizio Petrini, and John A. Gunnels. Scalable community detection with the louvain algorithm. 2015 IEEE International Parallel and Distributed Processing Symposium , pages 28–37, 2015

    2015

  48. [56]

    Understanding and bridging the gaps in current gnn perfor- mance optimizations

    Kezhao Huang, Jidong Zhai, Zhen Zheng, Youngmin Yi, and Xipeng Shen. Understanding and bridging the gaps in current gnn perfor- mance optimizations. Proceedings of the 26th ACM SIGPLAN Sympo- sium on Principles and Practice of Parallel Programming , 2021

    2021

  49. [57]

    Çatalyürek, Srinivasan Parthasarathy, and P

    Changwan Hong, Aravind Sukumaran-Rajam, Bortik Bandyopadhyay, Jinsung Kim, Süreyya Emre Kurt, Israt Nisa, Shivani Sabhlok, Ümit V. Çatalyürek, Srinivasan Parthasarathy, and P. Sadayappan. Efficient sparse-matrix multi-vector product on gpus. Proceedings of the 27th Internation...

    2018

  50. [58]

    A row decomposition-based approach for sparse matrix multiplication on gpus

    Meng Pang, Xiang Fei, Peng Qu, Youhui Zhang, and Zhaolin Li. A row decomposition-based approach for sparse matrix multiplication on gpus. Proceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming , 2024

    2024

  51. [59]

    Exploiting nvidia ampere structured sparsity with cusparselt

    NVIDIA. Exploiting nvidia ampere structured sparsity with cusparselt. NVIDIA Technical Report, 2020-002, 2020. 13

    2020

Pith tools

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