REVIEW 3 major objections 5 minor 17 references
Design of a Large Area Digital SiPM with High Fill Factor and Fully Serial Digital Readout for Single Photon Detection in Liquid Noble Gas Detectors
T0 review · 3 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash
Pith's one-line read This paper presents a prototype "digital SiPM" that reaches a 72.5% photo-sensitive fill factor on an 8x9 mm die and writes every photon hit as an x-y-t packet on a single serial line.
desk verdict A solid and honest engineering paper on a large-area digital SiPM with a genuinely clever four-wire serial readout; the cryogenic DCR numbers are vendor-supplied, not measured, which is the one big caveat. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing mechanism is the purely serial, packet-based readout chain together with the matrix scanner. Instead of analogue sums, every pixel reports through a wired-NOR and a hit flip-flop; column and row priority encoders turn any pattern of fired pixels into address words, and a global Gray counter timestamps hits with $\sim10~\mathrm{ns}$ granularity. A 28-bit serial packet uses a leading high level plus a flag: an empty packet can be claimed by any chip in the chain, which flips the flag and inserts its own 10-bit position, 10-bit time, and 6-bit chip ID. The design also uses a fill-factor formula, trading SPAD side length against the probability that a defect makes a SPAD unusable, to choose pixel geometry and to justify individual SPAD disable lines.
What would settle it
Cool the fabricated chip to liquid-xenon and liquid-argon temperatures, bias the SPADs at the intended overvoltage, and measure the dark count rate per square millimeter and the nearest-neighbour crosstalk fraction; if the measured rate is materially above about $0.02$ per second per square millimeter at liquid-xenon temperature or about $0.01$ at liquid-argon temperature, or crosstalk exceeds about 4%, the noise-coincidence background would dominate the rare-event signal and the central feasibility claim would fail.
Extended reading notes
Core claim
On the paper's own terms, the discovery is that a large-area digital SiPM can combine high fill factor, single-photon sensitivity, and a fully digital readout without amplifiers or ADCs. Each of the $32\times30$ logical pixels contains nine individually disable-able SPADs whose ORed hits set a flip-flop; a column-wise time latch captures the arrival time from a Gray counter, and a state machine scans only active columns and rows, writing $(x,y,t)$ words into a FIFO. Output uses a fixed 28-bit serial packet: a chip with data flips the empty packet flag and inserts its own position, time, and chip-ID payload, so daisy-chained chips merge onto one serial line at up to 1.8 million hits per second. The die has 72.5% photo-sensitive fill factor, and the authors estimate that wire-bonded or TSV/bump-bonded modules can reach plane fill factors of about 69–71%, which they compare with the 64.3% maximum packing of 3-inch PMTs. The first measurements, taken on a wafer prober, show the digital chain and register access working and confirm hit detection under a masked light spot.
Load-bearing premise
Everything rests on the foundry SPADs really having the quoted dark count rate of about $0.02$ events per second per square millimeter at liquid-xenon temperature and $0.01$ at liquid-argon temperature, with under 4% crosstalk; if real dark counts are higher, random coincidences would swamp the rare-event signature the chip is designed to catch.
Editorial extensions
If this is right
- Liquid noble gas detector planes can be assembled from many daisy-chained chips with one serial chain, reducing the number of cables, amplifiers, and ADCs compared with PMT-based designs.
- At a 50 MHz clock, one serial chain saturates at 1.8 million hits per second, while the expected background of S1 events plus dark counts is only about 100 thousand hits per second per square meter.
- An S2 burst of about 1000 photons takes roughly 0.5 milliseconds to read out, and pixels waiting for readout are blind during that time; the authors propose adding double hit buffering if simulations show this loss matters.
- Module designs with through-silicon vias and bump bonding could cover a plane at about 71% photo-sensitive fill factor, above the ~64.3% maximum for hexagonally packed 3-inch PMTs.
- Because each SPAD can be disabled individually, a fatal defect costs only one ninth of a pixel area, which is what makes the large-pixel layout robust at realistic defect densities.
Reading between the lines
- The empty-packet mechanism is naturally unfair to downstream chips under heavy load; allocating empty slots in a weighted round-robin would make the bandwidth per chip predictable without changing the packet format.
- The readout chain is wavelength-agnostic, so the same packet architecture could be reused with SPAD processes tuned for visible or infrared single-photon counting, not just VUV liquid-noble scintillation.
- A detector-level trigger that reads out only candidate time windows would reduce S2-burst blind time and timestamp corruption, since the chip currently records continuously regardless of occupancy.
- If the quoted cryogenic dark count rates hold, the dominant background in such a detector would shift from photodetector dark noise to radioactive backgrounds from materials and surfaces, which would change future material-selection priorities.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript presents the design and first functional tests of a large-area digital SiPM chip fabricated in a 350 nm CMOS/SPAD process. The chip has an active area of about 8 mm × 8.7 mm, divided into 32 × 30 pixels, each containing nine individually maskable SPADs; the pixel electronics and readout are fully digital, requiring only four signals (CLK, CMD, SERIN, SEROUT) and supporting daisy-chaining of multiple chips. The reported fill factor is 72.5%, and a module concept gives about 69–71% sensitive area. The authors describe the pixel circuit, matrix readout, serial readout protocol, command encoding, and chip-control scheme in detail. First wafer-prober tests demonstrate digital control, serial bit transfer, and light-induced hits using a metal mask. The discussion claims the technology is suitable for liquid noble gas detectors because of low cryogenic dark count rate and low crosstalk, citing vendor test-chip data, and identifies readout limitations for S2 bursts that remain to be simulated.
Significance. If the underlying SPAD technology indeed provides the quoted cryogenic dark count rates (about 0.02 Hz/mm² in LXe and 0.01 Hz/mm² in LAr) and crosstalk below 4%, then this chip architecture could enable large detector planes with roughly 70% photosensitive area, far simpler cabling, and no analog front-end electronics, which is a meaningful step toward a scalable alternative to PMTs in liquid noble gas experiments. The design contains several useful innovations: the defect-density-based fill-factor optimization in Eq. (1), the grouping of nine individually disabled SPADs into one logical pixel, the ultra-compact shared logic for four pixels, and a fully serial readout and control protocol that supports chip identification and configuration through the data stream. The paper is honest about its current status, reporting only qualitative room-temperature tests and clearly flagging known limitations, but the central application claim nevertheless rests on unmeasured cryogenic parameters.
major comments (3)
- [Section 4 and Abstract] The abstract's claim that the chip 'may be used in experiments that need to detect rare scintillation events' rests entirely on vendor-supplied cryogenic dark count rates (about 0.02 Hz/mm² at LXe temperature and 0.01 Hz/mm² at LAr temperature) and crosstalk of about 4% from a paper in preparation, not on measurements of this chip. Since the introduction itself sets a DCR requirement of ≤ 0.01 Hz/mm², the feasibility argument is load-bearing. If the actual DCR of these large SPADs at 165 K or 87 K is a few times higher, the dark-noise coincidence rate in a large detector plane would overwhelm the S1 signal. The paper should either present cryogenic DCR and crosstalk data for this specific chip or explicitly rephrase the application claim as conditional on future characterization. As written, the abstract overstates readiness.
- [Section 3] The first chip test results are qualitative wafer-prober checks performed at a few MHz. They demonstrate that the digital control, serial readout, and light-induced hit generation work, but they do not quantify dark count rate, photon detection efficiency, timing resolution, or crosstalk, even at room temperature. Given that the title advertises 'Single Photon Detection in Liquid Noble Gas Detectors', a room-temperature DCR measurement and a calibration of the 10 ns timestamp would materially substantiate the central functionality; without them, the paper validates the digital architecture, not the single-photon detection performance asserted in the title.
- [Sections 2.3 and 4] Two known limitations are acknowledged but not analyzed: (i) hits that arrive in a column after the first hit but before readout receive a timestamp that is too early, and (ii) during S2 burst readout, pixels waiting for readout are blind to new hits. The text states that the impact 'needs to be studied by simulations', which is honest, but these limitations are not mentioned in the abstract or the conclusions. For a design paper with application claims, the abstract should at least note that burst-mode efficiency remains to be verified, otherwise readers may assume the readout is fully lossless at high occupancy.
minor comments (5)
- [Section 2.1, Fig. 2] The figure caption says '10 random defects per mm²' for the left illustration, but the right plot shows curves for 0, 1, and 10 defects/mm²; please state explicitly which value the illustration uses.
- [Section 2.1] The choice of grouping nine SPADs into one logical pixel is motivated by defect tolerance and circuit reduction, but the average pixel size of 250 × 291 μm² and the individual SPAD active area are not given; please provide the per-SPAD dimensions.
- [Section 2.2] In the description of the hit flip-flop, the hit signal is said to be connected to the 'clock input' of an edge-triggered flip-flop. It would be clearer to state explicitly whether the hit signal is the clock or a data/set signal, since the text later says the flip-flop is 'set' by a hit.
- [Section 4.1, footnote 1] The comparison with the Hamamatsu R11410 PMT quotes a best hexagonal packing fill factor of ≤ 64.3%. Please double-check this number: using the stated diameters (76 mm outer, 65 mm active) and hexagonal packing of circles, the sensitive-area fraction is approximately 66%, so the quoted value may be slightly pessimistic.
- [Section 4] The bandwidth estimate of 1.8 Mhits/s for one serial chain assumes 50 MHz clock and 28-bit packets; the text correctly notes that the actual chip-to-chip protocol includes empty/full packet arbitration, but it would be helpful to state explicitly that this is an upper bound that does not account for packet overhead in a daisy chain.
Circularity Check
No significant circularity: the chip's performance claims follow from its concrete architecture and externally supplied technology parameters, not from fitting or self-citation.
full rationale
The paper's derivation chain is self-contained at the level it claims. The only measured input entering a design equation is the defect density used in Eq. (1) to choose the SPAD side length; this is a design optimization input, not a parameter fitted to data that is then reported as a predicted performance figure. The headline fill factor (72.5%) and readout throughput (1.8 Mhits/s at 50 MHz) are direct arithmetic consequences of the stated layout and the 28-bit serial packet protocol, respectively. The cryogenic DCR (≈0.02 Hz/mm² at LXe, ≈0.01 Hz/mm² at LAr) and crosstalk (≲4%) come from the Fraunhofer IMS test-chip technology and are explicitly attributed to an external, unpublished source ('paper in preparation'); they are inputs to the feasibility argument, not outputs derived from this chip. The open items stated in the paper — the S2 burst inefficiency ('needs to be studied by simulations') and the unpublished vendor DCR/crosstalk measurements — are evidence-quality limitations, not circular reasoning. No self-citation is used as a load-bearing justification, and no result is renamed as a prediction. Thus there is no circular step to exhibit, and the appropriate score is 0.
Assumptions & free parameters
free parameters (2)
- defect density epsilon =
not given, temperature dependent
- SPAD-to-SPAD gap d =
20 µm in illustrative model
assumptions (3)
- standard math Poisson statistics describe the distribution of fatal defects across SPADs
- domain assumption The Fraunhofer IMS SPAD technology has dark count rate approximately 0.02 Hz/mm² at LXe temperature and 0.01 Hz/mm² at LAr temperature, with crosstalk below 4%
- domain assumption The readout's handling of S2 bursts, with pixel blinding during readout and possible wrong time stamps, is acceptable for the target physics
Cite this review
Pith. "Pith review of Design of a Large Area Digital SiPM with High Fill Factor and Fully Serial Digital Readout for Single Photon Detection in Liquid Noble Gas Detectors." pith.science (2026). https://pith.science/paper/VKZLWPUX
@misc{pith2026250114083,
author = {Pith},
title = {Pith review of: Design of a Large Area Digital SiPM with High Fill Factor and Fully Serial Digital Readout for Single Photon Detection in Liquid Noble Gas Detectors},
year = {2026},
howpublished = {\url{https://pith.science/paper/VKZLWPUX}},
note = {Machine review of arXiv:2501.14083}
}
abstract
We present a 'digital SiPM' photo-detection chip combining single photon sensitive avalanche photo diodes and CMOS readout electronics on a single die. The chip has a size of $8046\times9032\,\mu m^2$ with $72.5\%$ of photo sensitive area. It is subdivided into $32\times30$ pixels with an average size of $250\times291\,\mu m^2$. For each photon hit, the chip records the pixel coordinate and the arrival time with a granularity of $\approx 10\,ns$. Readout and chip control are purely digital, requiring only 4 CMOS signals. Several chips can be daisy chained and grouped on larger modules so that detector planes with $\approx70\%$ photo sensitive area can be build. Our chip may be used in experiments that need to detect rare scintillation events, for instance dark matter searches using liquid noble gases.
Reference graph
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Reviewed August 10, 2026 · model on record in the stance chip above.
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