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An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator

T0 review · 3 major / 5 minor · reviewed 2026-08-09 · deepseek-v4-flash

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Pith's one-line read A fully digital 65 nm Tsetlin-machine accelerator classifies 28×28 images at 60.3k per second, using 8.6 nJ per classification and matching software accuracy on three datasets.

desk verdict First silicon CoTM ASIC with honest measurements, but the 8.6-nJ headline is core-only and the energy comparison needs re-scoping. read the letter →

arxiv 2501.19347 v3 pith:QVYP2FML submitted 2025-01-31 cs.LG cs.AR

Svein Anders Tunheim , Yujin Zheng , Lei Jiao , Rishad Shafik , Alex Yakovlev , Ole-Christoffer Granmo This is my paper · ORCID
classification cs.LGcs.AR
keywords TsetlinmachineASICacceleratorimageclassificationlow-powerinferencecoalescedconvolutionenergyper65nmCMOS
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to show that the Tsetlin machine, a learning algorithm based on Boolean logic rather than neural-network arithmetic, can be built as an all-digital accelerator chip that matches the energy efficiency of analog in-memory-computing designs. The manufactured 65 nm test chip classifies 28×28 greyscale images into ten classes at 60,300 images per second, using only 8.6 nJ per classification at a 0.82 V core supply, while reproducing software accuracy on three standard benchmarks. If correct, this puts logic-based machine learning in the same energy class as analog neural accelerators, with the practical advantage that a fully digital design ports to standard digital workflows and any CMOS process. The claim is bounded: the 8.6 nJ figure counts only core power, excluding a 3.3 V I/O block drawing 0.76 mW.

What carries the argument

The mechanism that carries the design is a clause pool with sequential-OR convolution: 128 clauses, each a conjunction of literals selected by Tsetlin automaton actions, are evaluated over 361 overlapping 10×10 patches, and a clause counts as fired for an image if it fired in any patch. Because every TA action bit and every signed class weight is held in registers (45,056 bits total), clause evaluation is combinational and the ten class sums are built by multiplexer-and-adder reduction trees with no multiplications, since clause outputs are 0 or 1. Two power-saving mechanisms are specific to this design: the clause switching reduction feedback (CSRF), which ORs the latched clause output into the clause's own combinational path so that a fired clause stops toggling, and separate clock domains with clock gating that stop the model registers (about 90% of the flip-flops) entirely during inference. CSRF cut the simulated combinational toggling rate by roughly half, though the measured total power reduction was under 1%, because the inference core's clock tree and DFFs dominate.

What would settle it

Measure total chip power (core plus 3.3 V I/O) during continuous classification at 27.8 MHz and 0.82 V, and divide by the 60,300 images/s rate; the paper's own numbers imply roughly 21 nJ per image on that boundary. If a system-level energy accounting is required for the comparative claims, this measurement refutes them against several mixed-signal comparators, and a second fully digital design reporting under 8.6 nJ on the same core-only metric would refute the 'lowest fully digital' claim directly.

Watch

Extended reading notes

Core claim

The paper reports a manufactured 65 nm CMOS accelerator that implements inference for the coalesced Tsetlin machine (CoTM) with a 10×10 sliding convolution window, applied to 28×28 booleanized images with ten classes. With 128 clauses sharing a single clause pool, all model state—34,816 Tsetlin automaton action bits and 10,240 signed 8-bit clause weights—sits in registers, so each of the 361 patches is evaluated by purely combinational clause logic in one clock cycle and class sums are built by addition-only reduction trees. Measured at 27.8 MHz and 0.82 V core supply, the chip classifies 60,300 images/s with 25.4 µs latency and 8.6 nJ per classification, producing test accuracies of 97.42% on MNIST, 84.54% on Fashion-MNIST, and 82.55% on Kuzushiji-MNIST, identical to the software models. The authors present this as the lowest energy per classification reported for a fully digital MNIST accelerator with comparable accuracy, and the second lowest overall among manufactured solutions, behind an analog time-domain CNN at 3.32 nJ. The design adds two power-saving mechanisms: the clause switching reduction feedback (CSRF), which stops re-evaluating clause logic once a clause has fired, and clock gating with separate clock domains for the static model and the active inference core.

Load-bearing premise

The headline energy figure counts only the accelerator core at a single operating point and excludes the test chip's 3.3 V I/O power, which at 0.76 mW adds roughly 12.6 nJ per image and would more than double the energy per classification under a full-system boundary.

Editorial extensions

If this is right

  • A Tsetlin-machine classifier now has a silicon-proven, fully digital implementation whose 8.6 nJ per classification is the lowest reported among fully digital MNIST accelerators with matching accuracy, putting logic-based learners in the same energy class as analog mixed-signal designs.
  • Because the design uses a standard synchronous digital flow, it can be re-targeted to other process nodes; the paper's estimates for a 28 nm port with literal-limited clauses put the core at 0.27 mm² and about 4.3 nJ per classification, close to the 3.32 nJ of the best analog solution.
  • For larger images, the architecture scales by composing specialized Tsetlin machines; the paper's TM Composites estimate for CIFAR-10 is 0.9 µJ per classification in 65 nm and 0.45 µJ in 28 nm, at an estimated 79% accuracy.
  • The measured accuracy exactly matches the software models, indicating that the register-based inference path introduces no accuracy degradation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The comparative claims are sensitive to the energy-accounting boundary: the paper's own measurements put the 3.3 V I/O block at 0.76 mW, which adds roughly 12.6 nJ per image at 60.3k images/s, so under a full-system boundary the 8.6 nJ figure becomes about 21 nJ and the 'lowest fully digital' claim would not survive against all comparators.
  • The near-zero measured benefit of the CSRF technique (under 1% power reduction) despite a simulated 50% drop in clause-logic toggling implies that the clause combinational logic is not the dominant energy consumer; future power gains would have to come from the clock tree and register storage.
  • The same 88% of TA actions that are 'exclude' states suggests a sparse model representation with literal addressing, as sketched for a 28 nm version, could cut roughly 47% of core area—a design change the paper estimates but does not fabricate.
  • The scaling estimates for 28 nm and for CIFAR-10 rest on Dennard scaling and linear area scaling with model size; a fabricated 28 nm port that deviates far from the predicted 4.3 nJ would point to those assumptions rather than to the architecture itself.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents the first fabricated ASIC based on the coalesced Tsetlin machine (CoTM) with convolution, implemented in 65 nm low-leakage CMOS. The accelerator stores all clause weights and Tsetlin-automaton action signals in registers, evaluates 128 clauses in parallel, and performs inference on booleanized 28x28 images with 10 classes. At 27.8 MHz and 0.82 V core supply, the authors measure 60.3k classifications/s, 0.52 mW core power, and 8.6 nJ per classification; test accuracies are 97.42% on MNIST, 84.54% on Fashion-MNIST, and 82.55% on Kuzushiji-MNIST, matching software models. The paper claims this is the lowest reported energy per classification among fully digital MNIST solutions and the second lowest overall, and it includes measured results, a comparison table, and estimates for scaled-up 28 nm and CIFAR-10 variants.

Significance. If the headline energy figure holds under a fair comparison, this is a useful silicon demonstration: it is the first manufactured CoTM ASIC, it is fully digital and tool-flow-compatible, the VHDL is publicly available, and the accuracy numbers are measured on independent test sets rather than simulated. The internal consistency of the measurements (0.52 mW / 60.3 kHz = 8.6 nJ at 0.82 V; 471 cycles at 27.8 MHz matching the reported throughput) is a strength. The significance is however conditional on the energy-accounting boundary used in the comparative claims, because the paper itself reports a separate 0.76 mW I/O power draw that is excluded from the headline figure.

major comments (3)
  1. [Section V, Table II, Table IV] The 8.6 nJ headline is a core-only measurement: Section V reports 0.52 mW accelerator-core power at 0.82 V and separately reports 0.76 mW consumed by the 3.3 V digital I/O pads in inference mode. Adding these gives 1.28 mW total chip power, or about 21.2 nJ per classification at 60.3k images/s, which is above the 12.92 nJ of [21] and far above the 3.32 nJ of [20]. The Introduction, Section VII, and Table IV use the 8.6 nJ value for the 'lowest fully digital' and 'second lowest overall' claims, so the comparison is load-bearing. The paper should report total measured chip EPC alongside the core-only value, or demonstrate that every comparator in Table IV is also core-only and excludes its I/O or interface power; the SoC-integration argument in Section V is a reasonable projection but is not a measurement on this chip.
  2. [Section V, Table II] The record claim rests on a single average measurement from one chip at one operating point (0.82 V, 27.8 MHz), with no error bars, repeated-measurement spread, or chip-to-chip variation reported. Because the paper claims the lowest reported EPC for a fully digital MNIST solution, the sensitivity of the EPC to supply voltage, clock frequency, and measurement repeatability should be quantified, and Table IV should state which numbers are single-chip measurements and which are multi-sample or simulated values.
  3. [Section VII, Table IV] The comparison in Table IV mixes measured and estimated data without a clear accounting boundary for energy. In particular, the 'This work scaled to 28 nm' column reports 4.3 nJ as an estimate based on Dennard scaling and a literal-count assumption from Section VI-A, but it is presented in the same table as measured EPC values from other chips. This makes the 'second lowest overall' claim hard to reproduce. The table should visually separate measured results from projections, or the projections should be moved to the discussion.
minor comments (5)
  1. [Abstract and Section V] The abstract states that the chip 'consumes 8.6 nJ per classification' without the qualifier 'accelerator core only'; since Section V explicitly distinguishes core power from I/O power, the abstract and Introduction should carry the same qualification.
  2. [Table II] For the 1 MHz, 0.82 V row, the reported 21 uW core power and 2.27k images/s imply 9.25 nJ per classification, but the table lists 9.6 nJ; please reconcile or explain the discrepancy.
  3. [Section VI-A] The text says 'close to what is achieved for the SNN accelerator in [20]', but Table IV identifies [20] as a CNN accelerator, not an SNN; please correct this reference error.
  4. [Section III-C] The sentence following Eq. (5) writes the position-bit term as '(Y - WY) + (X - WY)', but the equation and the intended symmetry require '(Y - WY) + (X - WX)'; please correct the typo.
  5. [Section IV-D and Section V] The CSRF feedback is listed as a contribution and is claimed to reduce switching activity, but Section V reports that CSRF alone provides less than 1% measured power reduction; the paper should state explicitly that the benefit was verified mainly in toggling-rate simulation, not in end-to-end energy.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the accuracy and energy claims are direct measurements benchmarked against external datasets and prior published chips.

full rationale

The paper's central claims are empirical hardware results, not derivations from premises that already contain the conclusions. Test accuracies (97.42% MNIST, 84.54% Fashion-MNIST, 82.55% KMNIST) are obtained by running the manufactured ASIC on standard external test sets and match the software models loaded into the chip; this is a verification of implementation correctness, not a prediction derived from a fitted quantity. The 8.6 nJ/frame EPC is computed from measured core power (0.52 mW at 0.82 V, 27.8 MHz) divided by measured throughput (60.3k images/s), with the measurement conditions explicitly stated. Comparisons in Table IV are against independently published accelerators [9, 20, 21], and no load-bearing claim rests on a uniqueness theorem or on a self-citation standing in for evidence. The design inherits modules from the authors' prior FPGA work [12] and uses the TMU software [41] for training, but both are public, independently accessible artifacts; using them as inputs is not circular because the paper's contribution is the silicon implementation and its measured behavior, not a re-derivation of those prior results. The only notable caveat is that the headline EPC excludes the measured 0.76 mW consumed by the 3.3 V digital I/O pads, so the 'lowest fully digital EPC' ranking is conditioned on a core-only accounting boundary. That is a metric-boundary and fairness-of-comparison concern, not an instance of a prediction reducing to its own inputs by construction. No fitted parameter is renamed as a prediction, no equation is equivalent to its input by definition, and no self-citation supplies the logical force of the central measured claim.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The central claim rests on a small configured TM model (128 clauses, 10x10 window, 8-bit weights), on standard TM inference equations, and on a core-only energy measurement. No new physical entities are introduced. The main unstated dependencies are the empirical validity of booleanization, the representativeness of the single-chip power measurement, and the completeness of the comparison table.

free parameters (6)
  • Number of clauses = 128
    Configuration choice: more clauses would raise accuracy but increase register storage and energy; the 128-clause model is the one trained and measured.
  • Convolution window size and stride = 10x10, stride 1
    Defines 136 feature bits per patch plus 18 position bits each for x and y, giving 272 literals per patch. Inherited from prior CTM work [13].
  • MNIST booleanization threshold = 75 (pixel value)
    Threshold chosen following [13]; affects the binarized input distribution and therefore measured accuracy.
  • Weight bit width = 8 bits signed
    Weights clipped to 8-bit two's complement to fit registers; the paper reports accuracy matches unquantized software, but the clip limits are a design choice.
  • Energy measurement operating point = 0.82 V, 27.8 MHz, clock-gating and CSRF enabled
    The 8.6 nJ figure is tied to this point; at 1.20 V the same chip consumes 19.1 nJ per classification.
  • FMNIST/KMNIST booleanization = adaptive Gaussian thresholding, parameters not stated
    Preprocessing method from [13]; exact parameters are not given in the paper, making those accuracy numbers less directly reproducible.
assumptions (4)
  • domain assumption Clause conjunction, weighted class sums, and sequential OR over patches (Eqs. 2, 3, 4, 6) define the classifier the hardware implements.
    The chip's accuracy equivalence to software assumes these TM equations are correctly mapped to logic; standard in the TM literature.
  • domain assumption Booleanization and thermometer position encoding preserve sufficient information for the reported accuracies.
    No proof is given that thresholding at 75 or adaptive Gaussian thresholding keeps all class-discriminative information; this is validated empirically by the software models.
  • domain assumption The Joulescope power measurements and continuous-mode classification rate are representative of the chip's steady-state operation.
    Single-chip average measurements without error bars or PVT sweeps underpin the headline EPC.
  • domain assumption Comparison EPC values from prior works [9], [20], [21], [11] are measured under comparable conditions.
    The 'second most energy-efficient' and 'lowest fully digital' rankings inherit the accuracy of external reports and assume fair comparison across technology nodes and design styles.

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Cite this review

Pith. "Pith review of An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator." pith.science (2026). https://pith.science/paper/QVYP2FML

@misc{pith2026250119347,
  author       = {Pith},
  title        = {Pith review of: An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QVYP2FML}},
  note         = {Machine review of arXiv:2501.19347}
}
abstract

We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28$\times$28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm$^2$. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 $\mu$s which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models.

Figures

Figures reproduced from arXiv: 2501.19347 by the authors.

Figure 1
Figure 1. A Tsetlin Automaton (TA) for two-action environments. One team of TAs is applied per clause, and the different TA actions are obtained during the training process, which involves feedback mechanisms to each TA [10]. For an inference-only solution, as reported in this paper, only the TA action signals from the trained model are needed, not the complete TAs. In a TM, the number of clauses, n, is a user specified integ… view at source ↗
Figure 2
Figure 2. ConvCoTM accelerator ASIC block diagram. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Register structure for window sliding. Each square represents a DFF. The first 10 rows of a booleanized image have been loaded and the window is in the start position (0,0). are 19 different x-coordinates for the window, requiring 18 bits. When the window has been evaluated at the rightmost x-position (0, 18), the contents of all 10 rows are shifted upwards with one step, and the next image datarow is loaded into th… view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: Circuitry for a single clause. Literals are denoted with [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 6
Figure 6. Figure 6: The argmax module, that selects the label corresponding to the largest class sum. Based on a submodule circuit from [11] [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: shows a simplified state diagram of the accelerator, and pseudo-code for the inference procedure is described in Algorithm 1 [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Simplified accelerator timing diagram. F. Clock Domains The key to reducing the digital switching power of the accelerator, lies at the top level of the ASIC architecture. Two separate clock domains are utilized, each with its own dedicated clock pin, assigned to the m…
Figure 9
Figure 9. Figure 9: Photo and layout plot of the ConvCoTM accelerator chip. [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: Test setup with the ConvCoTM ASIC test board connected to the [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]
Figure 11
Figure 11. Figure 11: , one could achieve a total reduction of the core area of approximately 47%. A reduction in chip area and EPC can be achieved by implementing the ConvCoTM accelerator in a more advanced technology. We here estimate the chip area, power consump￾tion and EPC if a 28 nm …

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Forward citations

Cited by 1 Pith paper

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Pith tools

Reviewed August 9, 2026 · model on record in the stance chip above.