Paper Citation Record · LEDGER

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

As of 11 August 2026, this Paper Citation Record lists 36 of 36 outbound references and 0 inbound Pith citation observations for arXiv:2502.00028.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2502.00028 v1

Coverage vector

measured 36 of 36 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-10T16:58:07.029237Z

measured 36 of 36 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-11T06:34:44.6726+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

36 of 36 outbound references displayed

verified exact0
verified fuzzy21
unresolved15
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation b7093240-ab6c-4c0a-84fe-ebfa0e99a476 · outbound

This paper cites Competition-level code generation with AlphaCode,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Competition-level code generation with AlphaCode,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.861271Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 2803b0bd-5706-476f-a255-e2aeaec39a59 · outbound

This paper cites Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.851149Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 627e2d81-9841-4654-b030-40b7441c8b33 · outbound

This paper cites Machine learning in advanced IC design: A methodological survey,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Machine learning in advanced IC design: A methodological survey,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.845381Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 7e9da787-bbc1-4f5f-adb2-f6460e9d9bb6 · outbound

This paper cites LLM-Aided Efficient Hardware Design Automation.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency LLM-Aided Efficient Hardware Design Automation

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.861949Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 604e7b5f-01d4-480e-91b7-5835acb3289b · outbound

This paper cites Chang et al.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Chang et al

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.867242Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a71f55a3-c91e-4026-b83f-0f648472c0e3 · outbound

This paper cites an unresolved cited work.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Unresolved cited work

Reference 6

Resolution: unresolved; raw_fallback, observed 2026-08-10T16:58:07.829495Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 6adb2abd-946c-474b-81c6-ae3ebb331f6f · outbound

This paper cites Chip-Chat: Challenges and Opportunities in Conversational Hardware Design.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.878152Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cf89072c-e25a-40cb-a0d6-fb9eef4ccea4 · outbound

This paper cites BetterV: Controlled verilog generation with discriminative guidance,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency BetterV: Controlled verilog generation with discriminative guidance,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.814352Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation e1d3f5d1-3747-4176-9e33-779c4bf5215b · outbound

This paper cites VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.890705Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e21a49e5-5924-4142-b78f-31ffcb011f8d · outbound

This paper cites Evaluating Large Language Models Trained on Code.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Evaluating Large Language Models Trained on Code

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.897536Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6897fc08-5fb0-4c3d-b813-11c8c4989cb8 · outbound

This paper cites Large language models for EDA: Future or mirage?.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Large language models for EDA: Future or mirage?

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.798829Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 17b98f96-280d-477b-95dc-99d015c25a3b · outbound

This paper cites DA VE: Deriving automatically verilog from english,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency DA VE: Deriving automatically verilog from english,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.781765Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation c68d8d40-6e50-4334-8b9f-157d47d58147 · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.912772Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 588a83b6-074b-409a-aa35-62ec33f7a660 · outbound

This paper cites Benchmarking large language models for automated verilog RTL code generation,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Benchmarking large language models for automated verilog RTL code generation,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.765508Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 5eab1210-ce69-40b4-9d55-d803e0ff730e · outbound

This paper cites CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.922350Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f29525f1-1b7c-47ce-8a3e-fcd18042d7b9 · outbound

This paper cites RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.926819Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 65a50014-beea-4df7-804b-0aec962c85b6 · outbound

This paper cites OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.931196Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e463ae52-0cab-4501-a644-65d0ab57883b · outbound

This paper cites AutoVCoder: A systematic framework for automated verilog code generation using LLMs,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency AutoVCoder: A systematic framework for automated verilog code generation using LLMs,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.749227Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 5c18d573-e21e-4c62-8fda-06d49124bdb8 · outbound

This paper cites , GPT-4 technical report , Mar.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency , GPT-4 technical report , Mar

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.733825Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 148b627a-3478-4090-b5fd-77e52848185e · outbound

This paper cites Improving large language model hardware generating quality through post-LLM search,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Improving large language model hardware generating quality through post-LLM search,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.719236Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation b7de1065-6401-4148-b380-cad8d9394c29 · outbound

This paper cites an unresolved cited work.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Unresolved cited work

Reference 21

Resolution: unresolved; raw_fallback, observed 2026-08-10T16:58:07.703938Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 180622b8-9a97-4ce9-9f60-ac6c111f1654 · outbound

This paper cites Retrieval-augmented generation for knowledge- intensive NLP tasks,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Retrieval-augmented generation for knowledge- intensive NLP tasks,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.687842Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 6798ad41-e677-4613-8e06-7176355df969 · outbound

This paper cites Thakur, J.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Thakur, J

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.670833Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation dc370711-a111-4c91-8c19-638cfe9fa5a5 · outbound

This paper cites Au- toBench: Automatic testbench generation and evaluation using LLMs for HDL design,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Au- toBench: Automatic testbench generation and evaluation using LLMs for HDL design,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.653954Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 16ce1470-2220-4aa7-a4df-d9ef3ede9f0e · outbound

This paper cites Self-consistency improves chain of thought reason- ing in language models,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Self-consistency improves chain of thought reason- ing in language models,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.637072Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 6934ff53-ea16-48f2-9a53-46a3f51c0dba · outbound

This paper cites Segmental minimum bayes-risk ASR voting strategies,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Segmental minimum bayes-risk ASR voting strategies,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.621372Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation cb0aa8d3-6785-4d2d-b3a5-6c5b563a68c5 · outbound

This paper cites A post-processing system to yield reduced word error rates: Recognizer output voting error reduction (ROVER),.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency A post-processing system to yield reduced word error rates: Recognizer output voting error reduction (ROVER),

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.604350Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation fa0459dc-5512-4088-aed9-6c54de6980dc · outbound

This paper cites Minimum bayes-risk decoding for statistical machine translation,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Minimum bayes-risk decoding for statistical machine translation,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.588057Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 94083977-565e-4b73-b492-7bb840533239 · outbound

This paper cites Bleu: A method for automatic evaluation of machine translation,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Bleu: A method for automatic evaluation of machine translation,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.568961Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 2b8d7650-3614-417d-8d60-ddfff06e02cc · outbound

This paper cites Chain-of-Thought Prompting Elicits Reasoning in Large Language Models.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Chain-of-Thought Prompting Elicits Reasoning in Large Language Models

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:07.003653Z

Source-reported events for the cited work

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Observation 3c1da549-02f4-4d88-82ef-fedac5301093 · outbound

This paper cites VerilogEval: Evaluating large language models for verilog code generation,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency VerilogEval: Evaluating large language models for verilog code generation,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.550404Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 76f96a91-7f3d-4a67-b039-6a1bfcbe0227 · outbound

This paper cites Steveicarus/iverilog.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Steveicarus/iverilog

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.533334Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 696ee5e4-257b-4165-8bce-4820eb7a17ee · outbound

This paper cites Huggingface transformers.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency Huggingface transformers

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.515703Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation c5c7233f-b0de-4885-8766-27656872e963 · outbound

This paper cites The Llama 3 Herd of Models.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency The Llama 3 Herd of Models

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:07.023966Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c94d3be8-5bcc-425e-8784-c2d7984f37bb · outbound

This paper cites AWQ: Activation-aware weight quantization for on-device LLM compression and acceleration,.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency AWQ: Activation-aware weight quantization for on-device LLM compression and acceleration,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T16:58:07.499030Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.

Observation 00770345-3436-4d3d-9503-7c901f6f4ad4 · outbound

This paper cites AutoChip: Automating HDL Generation Using LLM Feedback.

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency AutoChip: Automating HDL Generation Using LLM Feedback

Reference 2024

Resolution: unresolved; no resolver link, observed 2026-08-10T16:58:06.967807Z

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Unavailable: canonical work link unavailable.

Pith citing papers

No inbound Pith citation observations are available.