Pith. sign in

REVIEW 5 major objections 5 minor 57 references

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads

T0 review · 5 major / 5 minor · reviewed 2026-08-09 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read Lama claims DRAM can run bulk multiplications with one activation command per batch of lookups sharing a scalar operand.

desk verdict Genuinely new idea for LUT-based PuM, but the central hardware premise—per-mat independent column selection—is asserted without circuit support, and all quantitative claims ride on it. read the letter →

arxiv 2502.02142 v1 pith:4WGAB6MH submitted 2025-02-04 cs.AR

Bahareh Khabbazan , Marc Riera , Antonio González This is my paper · ORCID
classification cs.AR
keywords processing-using-memoryLUT-basedcomputingDRAMmat-levelparallelismHBM2bulkmultiplicationin-memoryacceleratorexponentialquantizationtransformerinference
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Lama is a lookup-table (LUT) processing-using-memory design that tries to remove the dominant energy cost of in-DRAM arithmetic: the repeated activation (ACT) command. Its central idea is to let each mat of a DRAM subarray select its own column inside an already-open row, so that one ACT command opens a row indexed by a scalar operand and then many lookups for different vector elements reuse that open row. The paper argues this works without changing DRAM timing parameters and extends cleanly to 8-bit operand pairs, where earlier LUT schemes had to decompose multiply into 4-bit pieces and shuffle partial results between subarrays. If correct, the result is a roughly fivefold reduction in memory commands versus the pLUTo baseline, an average 8.5x performance gain over prior PuM architectures and CPU, and an area overhead of only 2.47%. The same mechanism is packaged as LamaAccel, an HBM accelerator for attention-based models that uses exponential quantization to replace dot-product multiply-accumulates with addition and counting.

What carries the argument

The central mechanism is per-mat column independence inside a subarray, realized by replicating the column-address counter/latch for each of the 16 mats in an HBM2 bank and driving each mat's Column Select Lines with its own address. On top of this sits the operand-coalesced batch abstraction (scalar a indexes the LUT row, vector b_i indexes columns) and the open-page policy, which keeps that row live across many LUT retrieval commands. The mask logic, a multiplexer whose select lines come from the MSBs of b_i and the operand precision, filters valid results when an 8-bit LUT spans eight mats, and a temporary buffer serializes partial results until a full 16-byte output is formed. This combination is what lets one ACT command serve an entire batch and what removes the need for inter-subarray decomposition at higher precision.

What would settle it

Measure or simulate the column-select path of a real HBM2 bank and show that the Column Select Lines are driven by a single shared decoder word that cannot be overridden per mat; then two mats programmed with different column addresses in the same activated row would still return the same data, and the replicated counters would be unable to produce the p=16 or p=2 parallel lookups the paper claims. A circuit-level demonstration that per-mat column addressing violates tCCD or tFAW constraints would also settle the question.

Watch

Extended reading notes

Core claim

The paper's claim is that the energy cost of LUT-based in-memory computation is not intrinsic to the LUT access but to the number of row activations, and that this cost can be amortized. Lama organizes work into operand-coalesced batches: a scalar operand a is fixed across a vector of operands b_i. The value of a selects the row of the multiplication table; the values b_i select column positions. By adding 16 replicated column-address counter/latch units per bank, one per mat, Lama lets each mat read a different column of the same activated row, so a batch of up to 16 (4-bit) or 2 (8-bit) multiplications is served by one ACT plus a few reads. When the LUT for 6- to 8-bit operands spans multiple mats, mask logic picks the valid result out of each mat group, and the two internal column accesses needed to fetch a 16-bit product are handled by incrementing the column address. The paper further claims this design stays within standard DRAM timing, costs 2.47% area, and that for the 1024-multiplication test the ACT count is 8 versus 1088 for pLUTo at INT4 and 4352 at INT8.

Load-bearing premise

The design assumes a commodity HBM2 bank can give each of its 16 mats an independent column address by adding one replicated counter/latch per mat, without altering the shared Column Select Line structure or the standard DRAM timing; if the mats physically share a single column-select word, all mats would read the same column, and the claimed parallelism and single-ACT amortization would not materialize.

Editorial extensions

If this is right

  • ACT energy, which dominates DRAM access energy, is paid once per scalar-vector batch instead of once per lookup, so bulk multiplications that share a scalar operand become substantially cheaper.
  • 8-bit operand pairs can be multiplied in memory without decomposing into 4-bit pieces or moving partial products between subarrays, removing the main scalability barrier for LUT-based PuM.
  • Because the added logic sits at the bank periphery and does not change DRAM timing, the architecture could be adopted without changing the memory command interface.
  • When vector b spans multiple rows, additional ACTs are only needed for those rows, so the command savings scale with row reuse.
  • For attention models, replacing MACs with exponent counting via exponential quantization turns the bottleneck into counting operations that match Lama's strength, yielding 4-9x energy reductions over TPU/GPU baselines.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A consequence the paper does not pursue is that the same per-mat column mechanism could accelerate other column-selection-bound operations, such as bulk gathers, database table lookups, or histogramming, whenever one index is common across a batch.
  • The single-ACT amortization should grow with batch size, so workloads with long rows of reused activations such as large matrix multiplications would benefit more; testing batch sizes below the 128-element threshold mentioned in the paper would reveal the tFAW-limited regime.
  • The mask logic approach also suggests a natural extension to operand widths beyond 8 bits by increasing the number of mats per LUT and the mask-select bits, at the cost of proportionally lower parallelism.
  • If per-mat column addressing is physically viable, the same mechanism could apply to other memory technologies with mat-like organizations, not just HBM2.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper proposes Lama, a LUT-based processing-using-memory (PuM) architecture that aims to reduce ACT-command energy for bulk SIMD arithmetic by leveraging DRAM mat-level parallelism and the open-page policy. The key idea is to replicate the column-address counter/latch per mat so that each mat can select a different column of the activated row, enabling a single ACT command to serve multiple LUT accesses for operand-coalesced batches. The paper claims support for up to 8-bit operand pairs without decomposition, with only 2.47% area overhead, and reports large speedups and energy savings over pLUTo, SIMDRAM, CPU, GPU, and TPU baselines. It also introduces LamaAccel, an HBM-based accelerator for attention models that combines Lama with exponential quantization (DNA-TEQ) to replace multiplications with counting operations.

Significance. If the underlying hardware assumption were valid, the paper would address a real and important bottleneck in LUT-based PuM: the high energy cost of repeated ACT commands during LUT retrieval. The batching scheme and the emphasis on mat-level parallelism are conceptually interesting, and the idea of using exponent counting to avoid in-memory accumulation for LLM inference is a thoughtful application. However, the central mechanism rests on an unverified and, as described, physically questionable premise about independent per-mat column selection in commodity HBM2. The paper does not provide circuit-level evidence, and the reported quantitative results contain internal inconsistencies and rely on an unreleased simulator. The absence of a released artifact, unfair baseline choices in the LamaAccel evaluation, and incomplete area accounting further weaken the confidence in the claimed gains.

major comments (5)
  1. [Section III-A] The paper asserts that replicating the column-address counter/latch per mat 'enables independent column selection across all mats,' but it does not explain how the column-select lines (CSLs) are replicated or driven independently. In a commodity HBM2 bank, a single column address is decoded globally and the CSL word is shared across all mats in the subarray; replicating the counter/latch alone changes the address source but not the shared decode and drive path. Without a per-mat column decoder and independent CSL routing, all mats will still select the same column, so the parallelism degrees in Table I (p=16 for 4/5-bit and p=2 for 8-bit) collapse to p=1. The paper needs a concrete circuit design (schematic, routing, timing) or a supporting reference before the single-ACT amortization argument in Section IV can be accepted.
  2. [Section IV-E and Table IV] The 2.47% area overhead calculation omits the hardware that independent per-mat column selection would require. The area table includes replicated counters, one mask logic unit, and one temporary buffer per bank, but not per-mat column decoders, CSL drivers, or the additional CSL routing. It also does not account for the tri-state buffers per mat introduced in Section IV to isolate local row buffers; with 16 mats per subarray and 64 subarrays per bank, the 19.73 um^2 'Others' entry cannot plausibly cover these additions. The overhead claim is therefore not substantiated.
  3. [Section IV-F and Table V] Several quantitative claims are internally inconsistent. The abstract's 8.5x 'over state-of-the-art PuM architectures' is the average of the 3.8x speedup over pLUTo and the 13.7x speedup over SIMDRAM, which is not a meaningful single-baseline comparison. The '8x energy savings over CPU' in Section IV-F contradicts Table V, which gives 7900 nJ / 118.8 nJ ≈ 66.5x. The Conclusions' 'fivefold' command reduction is also inconsistent with the 14.7x–19.4x total-command reduction shown in Table V. These discrepancies need to be corrected before the results can be assessed.
  4. [Section V-D] The LamaAccel comparison against pLUTo is not fair. pLUTo is forced to operate at uniform 4-bit precision because it cannot support higher precisions, and the authors explicitly state that this may violate the <1% accuracy-loss constraint, while LamaAccel runs at the higher average precisions reported in Table VI. The claimed 1.7x average speedup and 4x energy savings over pLUTo therefore reflect a baseline at a different accuracy point and do not support the conclusion that LamaAccel is superior on equivalent terms. A fair comparison would need to hold the accuracy constraint fixed for both schemes.
  5. [Section IV-D] All performance and energy numbers come from an in-house simulator that is not released and is not validated against prior simulators or measured hardware. The central claims—single ACT per batch and the command counts in Table V—depend entirely on this simulator. The paper should provide a detailed analytical model (equations for command count, latency, and energy) and a sensitivity analysis for parameters such as tFAW, row size, and bank count, so that the results can be checked without relying on an unavailable artifact.
minor comments (5)
  1. [Section IV-B/IV-C] Sections IV-B and IV-C contain nearly identical text and duplicate Tables I and II; one of them should be removed.
  2. [Section III-B] The mask logic is said to be inspired by a 'mask logic circuit found in commodity DRAM' with citation [34], but [34] is the Micron DRAM Power Calculator, which is not an appropriate source for a circuit description.
  3. [Figure 9] The timeline figure would benefit from a clear definition of the 'M' block and the red block in the caption; without the main text, the figure is not self-explanatory.
  4. [Table VI] The table header uses 'Avg bit' while the text says 'average bitwidth'; please unify the terminology.
  5. [Section II-C] The accuracy guarantee of LamaAccel is inherited from the authors' DNA-TEQ scheme [25]; the paper should explicitly state that this is not a new property established in this work, and the quantization search code is not released.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity found: the central efficiency claims follow from an explicit architectural model, and the self-citations are building-block references backed by in-paper equations and measurements.

full rationale

The paper's derivation chain is not circular. Lama's single-ACT claim follows from an explicit data-layout and command model: rows are indexed by the scalar operand a and columns by vector elements b_i (Sec. III, Fig. 6), so one ACT opens a row containing f(a,b_i) and subsequent LUT retrievals are column accesses using the open-page policy. This is a design assertion about DRAM organization, not a fitted parameter renamed as a prediction nor a quantity defined in terms of the result it is supposed to predict. The 8-bit precision result similarly follows from the stated LUT size and mat budget (Table II), not from a self-referential fit. The claimed 2.47% area overhead is a synthesis-based accounting of the listed added components (Sec. IV-E), and the performance/energy numbers come from a command-counting simulator with stated HBM2 timing/energy parameters (Sec. IV-D). The main self-citation, DNA-TEQ [25], is used as a building block for LamaAccel's exponential quantization; the paper re-derives the expansion in Eq. (1) and reports measured quantized accuracies in Table VI, so the citation is not the sole support for a load-bearing claim. The admitted simplification of running the pLUTo baseline at uniform 4-bit precision (Sec. V-D) is a baseline-fairness caveat, not a circular reduction. No equation or parameter in the paper is shown to be equivalent to its own output by construction, so no circular step meeting the quoted-evidence bar is present.

Assumptions & free parameters 2 free parameters · 5 assumptions · 3 invented entities

The central claim rests on four substantive assumptions without independent validation: per-mat independent column selection, transfer of subarray-level tri-stating to HBM2, the open-page read model, and the inherited DNA-TEQ accuracy. Free parameters are the chosen counter bitwidth and the per-layer exponent bitwidths from the authors' quantization search. The hardware units proposed are simulated or synthesized only, not fabricated, so they carry no external confirmation.

free parameters (2)
  • Occurrence-counter bitwidth in LamaAccel = 8 bits
    Chosen after analyzing maximum exponent occurrence counts across the evaluated networks (Section V-B); not derived from first principles, so the counter-array area and parallelism depend on a fitted design choice.
  • Per-layer exponent bitwidth (DNA-TEQ search) = 3.48 to 6.45 bits average across tasks (Table VI)
    Determined by the DNA-TEQ quantization search algorithm from the authors' prior work [25] to keep accuracy loss below 1%; these precision values strongly influence LamaAccel's reported speedup and energy savings.
assumptions (5)
  • ad hoc to paper Each mat in an HBM2 subarray can be given an independent column address using only replicated column counters/latches, with shared CSL wiring or per-mat CSL routing unchanged and no timing impact.
    Invoked in Section III-A to enable parallel LUT retrieval; no circuit-level validation or prior implementation is cited for per-mat independent column selection.
  • domain assumption Multiple subarrays can keep rows open simultaneously without shorting the master data line because the tri-state buffer scheme of [28] transfers to HBM2's 16-mat organization.
    Used in Section IV to keep source and compute subarrays open at the same time (Figure 8); compatibility with HBM2 geometry is assumed.
  • domain assumption DRAM open-page policy permits an arbitrary number of column reads from an activated row before PRECHARGE, with no additional ACT energy.
    This is the basis for amortizing one ACT over an entire operand-coalesced batch (Section III, Figure 9).
  • domain assumption DNA-TEQ exponential quantization preserves task accuracy within 1% for BERT, BART, and GPT-2 on the listed tasks without fine-tuning.
    LamaAccel's functional validity is inherited from the authors' prior work [25], Table VI; not independently replicated in this paper.
  • domain assumption The in-house simulator's command counts and energy parameters (e.g., eACT=909 pJ, tFAW=12 ns) accurately model both Lama and the baselines.
    All quantitative claims in Section IV-F and V-E depend on this simulator; no validation against silicon or released artifact is provided.
invented entities (3)
  • Per-mat column counter/latch (16 per bank)
    purpose: Allows each mat to select a different column in the open LUT row, enabling p=16 or p=2 parallel lookups with one ACT.
    Central new hardware; synthesized only, no fabricated DRAM test, and wiring implications for CSL are not specified.
  • Mask logic (16:1 multiplexer, FSM, serial-in/parallel-out buffer)
    purpose: Filters invalid LUT results when a result spans multiple mats (bit-widths 6-8), restoring a fixed 16-byte output.
    New unit whose latency is modeled as an extra block in the timeline but not validated in a real DRAM.
  • LamaAccel sign-XNOR enhanced column counter with de-multiplexer
    purpose: Increments or decrements exponent occurrence counters in place based on sign products, enabling counting-based dot products.
    Extension of the column counter to perform accumulation in memory; no prototype or measurement.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads." pith.science (2026). https://pith.science/paper/4WGAB6MH

@misc{pith2026250202142,
  author       = {Pith},
  title        = {Pith review of: Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4WGAB6MH}},
  note         = {Machine review of arXiv:2502.02142}
}
read the original abstract

Data movement in memory-intensive workloads, such as deep learning, incurs energy costs that are over three orders of magnitude higher than the cost of computation. Since these workloads involve frequent data transfers between memory and processing units, addressing data movement overheads is crucial for improving performance. Processing-using-memory (PuM) offers an effective solution by enabling in-memory computation, thereby minimizing data transfers. In this paper we propose Lama, a LUT-based PuM architecture designed to efficiently execute SIMD operations by supporting independent column accesses within each mat of a DRAM subarray. Lama exploits DRAM's mat-level parallelism and open-page policy to significantly reduce the number of energy-intensive memory activation (ACT) commands, which are the primary source of overhead in most PuM architectures. Unlike prior PuM solutions, Lama supports up to 8-bit operand precision without decomposing computations, while incurring only a 2.47% area overhead. Our evaluation shows Lama achieves an average performance improvement of 8.5x over state-of-the-art PuM architectures and a 3.8x improvement over CPU, along with energy efficiency gains of 6.9x/8x, respectively, for bulk 8-bit multiplication. We also introduce LamaAccel, an HBM-based PuM accelerator that utilizes Lama to accelerate the inference of attention-based models. LamaAccel employs exponential quantization to optimize product/accumulation in dot-product operations, transforming them into simpler tasks like addition and counting. LamaAccel delivers up to 9.3x/19.2x reduction in energy and 4.8x/9.8x speedup over TPU/GPU, along with up to 5.8x energy reduction and 2.1x speedup over a state-of-the-art PuM baseline.

Figures

Figures reproduced from arXiv: 2502.02142 by the authors.

Figure 1
Figure 1. Different PuM techniques: (a) charge-sharing (b) LUT [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Decomposing a vector-matrix multiplication into [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. HBM2 Organization: (a) High-level, (b) Channel-level, [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (9 more)
Figure 4
Figure 4. Figure 4: Encoder and Decoder blocks in Attention-based mod [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Example of pLUTo for 4-bit multiplications. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: LUT data layout for (a) 4-bit and (b) 8-bit multiplica [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 7
Figure 7. Figure 7: Mask logic. b0,b16,... b15,b32,... Source subarray Local row-buffer b0, b16,... b1, b17, …, Compute subarray … f(0,0),…,f(0,15) f(1,0),…,f(1,15) … f(15,0),…,f(15,15) Local row-buffer f(a, 0), f(a, 1),… Mask Logic 1 15 Temp Buff b0 b1 b15 from the address register b0, b…
Figure 8
Figure 8. Figure 8: Detailed steps to perform bulk 4-bit multiplications [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: Timeline of performing multiplications using Lama. Each read operation includes two internal column accesses (ICA). [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: LamaAccel data layout. each pseudo-channel. For fully-connected (FC) layers whose weights are statically known, the weights are pre-stored in the banks. For matrix-multiplication operations inside the self￾attention blocks employing the K and V matrices, LamaAccel wri…
Figure 11
Figure 11. Figure 11: Counting the occurrence of exponents. TABLE VI: Baseline accuracy vs accuracy after performing exponential quantization for the evaluated LLM models. The average bitwidth is the mean each layer’s exponents. Network Task Baseline Acc Quantized Acc Avg bit max SL BERT-B…
Figure 13
Figure 13. Figure 13: Speedup and energy savings of LamaAccel normal [PITH_FULL_IMAGE:figures/full_fig_p016_13.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

57 extracted references · 44 canonical work pages

  1. [1]

    De- mystifying the characteristics of high bandwidth memory for real-time systems,

    K. Asifuzzaman, M. Abuelala, M. Hassan, and F. J. Cazorla, “De- mystifying the characteristics of high bandwidth memory for real-time systems,” in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) . IEEE, 2021, pp. 1–9

    work page 2021

  2. [2]

    Reconfigurable processing-in-memory architecture for data intensive applications,

    S. Bavikadi, P. R. Sutradhar, A. Ganguly, and S. M. P. Dinakarrao, “Reconfigurable processing-in-memory architecture for data intensive applications,” in 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID). IEEE, 2024, pp. 222–227

    work page 2024

  3. [3]

    Edge tpu system requirements,

    Coral, “Edge tpu system requirements,” https://coral.ai/docs/edgetpu/ compiler/

    work page

  4. [4]

    Edge tpu system-on-module (som),

    Coral.ai, “Edge tpu system-on-module (som),” https://coral.ai/products/ som/

    work page

  5. [5]

    Per- mdnn: Efficient compressed dnn architecture with permuted diagonal matrices,

    C. Deng, S. Liao, Y . Xie, K. K. Parhi, X. Qian, and B. Yuan, “Per- mdnn: Efficient compressed dnn architecture with permuted diagonal matrices,” in 2018 51st Annual IEEE/ACM international symposium on microarchitecture (MICRO). IEEE, 2018, pp. 189–202

    work page 2018

  6. [6]

    Dracc: A dram based accelerator for accurate cnn inference,

    Q. Deng, L. Jiang, Y . Zhang, M. Zhang, and J. Yang, “Dracc: A dram based accelerator for accurate cnn inference,” in Proceedings of the 55th annual design automation conference , 2018, pp. 1–6

    work page 2018

  7. [7]

    Lacc: Exploiting lookup table-based fast and accurate vector multiplication in dram-based cnn accelerator,

    Q. Deng, Y . Zhang, M. Zhang, and J. Yang, “Lacc: Exploiting lookup table-based fast and accurate vector multiplication in dram-based cnn accelerator,” in Proceedings of the 56th Annual Design Automation Conference 2019, 2019, pp. 1–6

    work page 2019

  8. [8]

    To pim or not for emerging general purpose processing in ddr memory systems,

    A. Devic, S. B. Rai, A. Sivasubramaniam, A. Akel, S. Eilert, and J. Eno, “To pim or not for emerging general purpose processing in ddr memory systems,” in Proceedings of the 49th Annual International Symposium on Computer Architecture, 2022, pp. 231–244

    work page 2022

Show all 57 references
  1. [9]

    Bert: Pre-training of deep bidirectional transformers for language understanding,

    J. Devlin, “Bert: Pre-training of deep bidirectional transformers for language understanding,” arXiv preprint arXiv:1810.04805 , 2018

    2018 arXiv

  2. [10]

    Neural cache: Bit-serial in-cache acceleration of deep neural networks,

    C. Eckert, X. Wang, J. Wang, A. Subramaniyan, R. Iyer, D. Sylvester, D. Blaaauw, and R. Das, “Neural cache: Bit-serial in-cache acceleration of deep neural networks,” in 2018 ACM/IEEE 45Th annual international symposium on computer architecture (ISCA). IEEE, 2018, pp. 383–396

    2018

  3. [11]

    pluto: Enabling massively parallel computation in dram via lookup tables,

    J. D. Ferreira, G. Falcao, J. G ´omez-Luna, M. Alser, L. Orosa, M. Sadrosadati, J. S. Kim, G. F. Oliveira, T. Shahroodi, A. Nori et al. , “pluto: Enabling massively parallel computation in dram via lookup tables,” in 2022 55th IEEE/ACM International Symposium on Microarchitect...

    2022

  4. [12]

    Computedram: In-memory compute using off-the-shelf drams,

    F. Gao, G. Tziantzioulis, and D. Wentzlaff, “Computedram: In-memory compute using off-the-shelf drams,” in Proceedings of the 52nd annual IEEE/ACM international symposium on microarchitecture , 2019, pp. 100–113

    2019

  5. [13]

    The processing-in-memory paradigm: Mechanisms to enable adoption,

    S. Ghose, K. Hsieh, A. Boroumand, R. Ausavarungnirun, and O. Mutlu, “The processing-in-memory paradigm: Mechanisms to enable adoption,” Beyond-CMOS Technologies for Next Generation Computer Design , pp. 133–194, 2019

    2019

  6. [14]

    Simdram: A framework for bit-serial simd processing using dram,

    N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. G ´omez-Luna, and O. Mutlu, “Simdram: A framework for bit-serial simd processing using dram,” in Proceedings of the 26th ACM International Conference on Architectural Supp...

    2021

  7. [15]

    Aˆ 3: Accelerating attention mechanisms in neural networks with approximation,

    T. J. Ham, S. J. Jung, S. Kim, Y . H. Oh, Y . Park, Y . Song, J.-H. Park, S. Lee, K. Park, J. W. Lee et al. , “Aˆ 3: Accelerating attention mechanisms in neural networks with approximation,” in 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)....

    2020

  8. [16]

    Eie: Efficient inference engine on compressed deep neural network,

    S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, M. A. Horowitz, and W. J. Dally, “Eie: Efficient inference engine on compressed deep neural network,” ACM SIGARCH Computer Architecture News , vol. 44, no. 3, pp. 243–254, 2016

    2016

  9. [17]

    Sal-pim: A subarray-level processing-in-memory architecture with lut-based linear interpolation for transformer-based text generation,

    W. Han, H. Cho, D. Kim, and J.-Y . Kim, “Sal-pim: A subarray-level processing-in-memory architecture with lut-based linear interpolation for transformer-based text generation,”arXiv preprint arXiv:2401.17005, 2024

    2024 arXiv

  10. [18]

    Newton: A dram-maker’s accelerator-in-memory (aim) architecture for machine learning,

    M. He, C. Song, I. Kim, C. Jeong, S. Kim, I. Park, M. Thottethodi, and T. Vijaykumar, “Newton: A dram-maker’s accelerator-in-memory (aim) architecture for machine learning,” in 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020, pp. 372–385

    2020

  11. [19]

    Teaching machines to read and comprehend,

    K. M. Hermann, T. Kocisky, E. Grefenstette, L. Espeholt, W. Kay, M. Su- leyman, and P. Blunsom, “Teaching machines to read and comprehend,” Advances in neural information processing systems , vol. 28, 2015

    2015

  12. [20]

    Intel ® xeon® w-2245 processor specifications,

    Intel, “Intel ® xeon® w-2245 processor specifications,” https://www.intel.com/content/www/us/en/products/sku/198609/ intel-xeon-w2245-processor-16-5m-cache-3-90-ghz/specifications. html

  13. [21]

    Near-memory com- puting on fpgas with 3d-stacked memories: Applications, architectures, and optimizations,

    V . Iskandar, M. A. A. E. Ghany, and D. Goehringer, “Near-memory com- puting on fpgas with 3d-stacked memories: Applications, architectures, and optimizations,” ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 1, pp. 1–32, 2022

    2022

  14. [22]

    Mnnfast: A fast and scalable system architecture for memory-augmented neural networks,

    H. Jang, J. Kim, J.-E. Jo, J. Lee, and J. Kim, “Mnnfast: A fast and scalable system architecture for memory-augmented neural networks,” in Proceedings of the 46th International Symposium on Computer Architecture, 2019, pp. 250–263

    2019

  15. [23]

    Jedec standard jesd235d: High bandwidth memory (hbm1, hbm2) dram specification,

    JEDEC, “Jedec standard jesd235d: High bandwidth memory (hbm1, hbm2) dram specification,” 2021

    2021

  16. [24]

    Keeth, R

    B. Keeth, R. J. Baker, B. Johnson, and F. Lin, DRAM circuit design: fundamental and high-speed topics. John Wiley & Sons, 2007, vol. 13

    2007

  17. [25]

    Dna-teq: An adaptive exponential quantization of tensors for dnn inference,

    B. Khabbazan, M. Riera, and A. Gonz ´alez, “Dna-teq: An adaptive exponential quantization of tensors for dnn inference,” in 2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC) . IEEE, 2023, pp. 1–10

    2023

  18. [26]

    An energy- efficient near-data processing accelerator for dnns to optimize memory accesses,

    B. Khabbazan, M. Sabri, M. Riera, and A. Gonzalez, “An energy- efficient near-data processing accelerator for dnns to optimize memory accesses,” Available at SSRN 4893869 , 2024

    2024

  19. [27]

    Neurocube: A programmable digital neuromorphic architecture with high-density 3d memory,

    D. Kim, J. Kung, S. Chai, S. Yalamanchili, and S. Mukhopadhyay, “Neurocube: A programmable digital neuromorphic architecture with high-density 3d memory,”ACM SIGARCH Computer Architecture News, vol. 44, no. 3, pp. 380–392, 2016

    2016

  20. [28]

    A case for exploiting subarray-level parallelism (salp) in dram,

    Y . Kim, V . Seshadri, D. Lee, J. Liu, and O. Mutlu, “A case for exploiting subarray-level parallelism (salp) in dram,” ACM SIGARCH Computer Architecture News, vol. 40, no. 3, pp. 368–379, 2012

    2012

  21. [29]

    Assessing merged dram/logic technology,

    Y .-B. Kim and T. W. Chen, “Assessing merged dram/logic technology,” Integration, vol. 27, no. 2, pp. 179–194, 1999

    1999

  22. [30]

    Fulcrum: A simplified control and access mechanism toward flexible and practical in-situ accelerators,

    M. Lenjani, P. Gonzalez, E. Sadredini, S. Li, Y . Xie, A. Akel, S. Eilert, M. R. Stan, and K. Skadron, “Fulcrum: A simplified control and access mechanism toward flexible and practical in-situ accelerators,” in 2020 IEEE International Symposium on High Performance Computer Arc...

    2020

  23. [31]

    Bart: Denoising sequence-to-sequence pre-training for natu- ral language generation, translation, and comprehension,

    M. Lewis, “Bart: Denoising sequence-to-sequence pre-training for natu- ral language generation, translation, and comprehension,” arXiv preprint arXiv:1910.13461, 2019

    1910 arXiv

  24. [32]

    Drisa: A dram-based reconfigurable in-situ accelerator,

    S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y . Xie, “Drisa: A dram-based reconfigurable in-situ accelerator,” in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017, pp. 288–301

    2017

  25. [33]

    Learning word vectors for sentiment analysis,

    A. L. Maas, R. E. Daly, P. T. Pham, D. Huang, A. Y . Ng, and C. Potts, “Learning word vectors for sentiment analysis,” in Proceedings of the 49th Annual Meeting of the Association for Computational Linguistics: Human Language Technologies , D. Lin, Y . Matsumoto, and R. Mihalc...

    2011

  26. [34]

    Dram power calculator,

    Micron, “Dram power calculator,” https://www.micron.com/ sales-support/design-tools/dram-power-calculator

  27. [35]

    Pro- cessing data where it makes sense: Enabling in-memory computation,

    O. Mutlu, S. Ghose, J. G ´omez-Luna, and R. Ausavarungnirun, “Pro- cessing data where it makes sense: Enabling in-memory computation,” Microprocessors and Microsystems, vol. 67, pp. 28–41, 2019

    2019

  28. [36]

    Abstractive text summarization using sequence-to-sequence rnns and beyond,

    R. Nallapati, B. Zhou, C. Gulcehre, B. Xiang et al. , “Abstractive text summarization using sequence-to-sequence rnns and beyond,” arXiv preprint arXiv:1602.06023, 2016

    2016 arXiv

  29. [37]

    Nvidia management library (nvml),

    NVIDIA, “Nvidia management library (nvml),” https://developer.nvidia. com/management-library-nvml

  30. [38]

    Fine-grained dram: Energy-efficient dram for extreme bandwidth systems,

    M. O’Connor, N. Chatterjee, D. Lee, J. Wilson, A. Agrawal, S. W. Keckler, and W. J. Dally, “Fine-grained dram: Energy-efficient dram for extreme bandwidth systems,” in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture , 2017, pp. 41–54

    2017

  31. [39]

    Fine-grained dram: Energy-efficient dram for extreme bandwidth systems,

    ——, “Fine-grained dram: Energy-efficient dram for extreme bandwidth systems,” in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017, pp. 41–54

    2017

  32. [40]

    Google coral edge tpu,

    qengineering, “Google coral edge tpu,” https://qengineering.eu/ google-corals-tpu-explained.html

  33. [41]

    Language models are unsupervised multitask learners,

    A. Radford, J. Wu, R. Child, D. Luan, D. Amodei, I. Sutskever et al., “Language models are unsupervised multitask learners,” OpenAI blog , vol. 1, no. 8, p. 9, 2019

    2019

  34. [42]

    Squad: 100,000+ questions for machine comprehension of text,

    P. Rajpurkar, J. Zhang, K. Lopyrev, and P. Liang, “Squad: 100,000+ questions for machine comprehension of text,” arXiv, 2016

    2016

  35. [43]

    Redy: A novel reram-centric dynamic quantization approach for energy-efficient cnns,

    M. Sabri Abrebekoh, M. Riera Villanueva, and A. Gonzalez, “Redy: A novel reram-centric dynamic quantization approach for energy-efficient cnns,” in Proceedings of the 53rd International Conference on Parallel Processing, 2024, pp. 1042–1051

    2024

  36. [44]

    Scale-sim: Systolic cnn accelerator simulator,

    A. Samajdar, Y . Zhu, P. Whatmough, M. Mattina, and T. Kr- ishna, “Scale-sim: Systolic cnn accelerator simulator,” arXiv preprint arXiv:1811.02883, 2018

    2018 arXiv

  37. [45]

    Ambit: In- memory accelerator for bulk bitwise operations using commodity dram technology,

    V . Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Ambit: In- memory accelerator for bulk bitwise operations using commodity dram technology,” inProceedings of the 50th Annual IEEE/ACM International Sympo...

    2017

  38. [46]

    The processing using memory paradigm: In-dram bulk copy, initialization, bitwise and and or,

    V . Seshadri and O. Mutlu, “The processing using memory paradigm: In-dram bulk copy, initialization, bitwise and and or,” arXiv preprint arXiv:1610.09603, 2016

    2016 arXiv

  39. [47]

    Recursive deep models for semantic compositionality over a sentiment treebank,

    R. Socher, A. Perelygin, J. Wu, J. Chuang, C. D. Manning, A. Y . Ng, and C. Potts, “Recursive deep models for semantic compositionality over a sentiment treebank,” in Proceedings of the 2013 conference on empirical methods in natural language processing , 2013, pp. 1631–1642

    2013

  40. [48]

    ppim: A programmable processor-in-memory architecture with precision-scaling for deep learning,

    P. R. Sutradhar, M. Connolly, S. Bavikadi, S. M. P. Dinakarrao, M. A. In- dovina, and A. Ganguly, “ppim: A programmable processor-in-memory architecture with precision-scaling for deep learning,” IEEE Computer Architecture Letters, vol. 19, no. 2, pp. 118–121, 2020

    2020

  41. [49]

    Hbm: Memory solution for high performance processors,

    K. Tran and J. Ahn, “Hbm: Memory solution for high performance processors,” MemCon. Santa Clara, CA, USA (Oct 2014) , 2014

    2014

  42. [50]

    Understanding the energy consumption of dynamic ran- dom access memories,

    T. V ogelsang, “Understanding the energy consumption of dynamic ran- dom access memories,” in 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 2010, pp. 363–374

    2010

  43. [51]

    Renew: Enhancing lifetime for reram crossbar based neural network accelerators,

    W. Wen, Y . Zhang, and J. Yang, “Renew: Enhancing lifetime for reram crossbar based neural network accelerators,” in 2019 IEEE 37th International Conference on Computer Design (ICCD) . IEEE, 2019, pp. 487–496

    2019

  44. [52]

    A broad-coverage challenge corpus for sentence understanding through inference,

    A. Williams, N. Nangia, and S. R. Bowman, “A broad-coverage challenge corpus for sentence understanding through inference,” arXiv preprint arXiv:1704.05426, 2017

    2017 arXiv

  45. [53]

    Transformers: State-of- the-art natural language processing,

    T. Wolf, L. Debut, V . Sanh, J. Chaumond, C. Delangue, A. Moi, P. Cistac, T. Rault, R. Louf, M. Funtowicz, J. Davison, S. Shleifer, P. von Platen, C. Ma, Y . Jernite, J. Plu, C. Xu, T. L. Scao, S. Gugger, M. Drame, Q. Lhoest, and A. M. Rush, “Transformers: State-of- the-art na...

    2020

  46. [54]

    Interstellar: Using halide’s scheduling language to analyze dnn accelerators,

    X. Yang, M. Gao, Q. Liu, J. Setter, J. Pu, A. Nayak, S. Bell, K. Cao, H. Ha, P. Raina et al., “Interstellar: Using halide’s scheduling language to analyze dnn accelerators,” in Proceedings of the Twenty-Fifth Interna- tional Conference on Architectural Support for Programming ...

    2020

  47. [55]

    Mokey: Enabling narrow fixed-point inference for out-of-the-box floating-point transformer models,

    A. H. Zadeh, M. Mahmoud, A. Abdelhadi, and A. Moshovos, “Mokey: Enabling narrow fixed-point inference for out-of-the-box floating-point transformer models,” in Proceedings of the 49th Annual International Symposium on Computer Architecture , 2022, pp. 888–901

    2022

  48. [56]

    Transpim: A memory- based acceleration via software-hardware co-design for transformer,

    M. Zhou, W. Xu, J. Kang, and T. Rosing, “Transpim: A memory- based acceleration via software-hardware co-design for transformer,” in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2022, pp. 1071–1085

    2022

  49. [57]

    Red-lut: Reconfigurable in- dram luts enabling massive parallel computation,

    R. Zhou, A. Roohi, D. Misra, and S. Angizi, “Red-lut: Reconfigurable in- dram luts enabling massive parallel computation,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design . IEEE, 2022, pp. 1–8

    2022

Pith tools

Reviewed August 9, 2026 · model on record in the stance chip above.