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REVIEW 2 major objections 5 minor 88 references

A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

T0 review · 2 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read A compiler backend organized as layered SSA intermediate representations can generate micro-kernels for a RISC-V accelerator that reach 90–95% FPU utilization without handwritten assembly.

desk verdict Solid systems paper: the multi-level SSA backend for RISC-V accelerators is real, reproducible, and the 90% utilization claim holds up; the unroll-factor concern is a minor footnote, not a flaw. read the letter →

arxiv 2502.04063 v1 pith:S7LOMCDF submitted 2025-02-06 cs.PL

Alexandre Lopoukhine , Federico Ficarelli , Christos Vasiladiotis , Anton Lydike , Josse Van Delm , Alban Dutilleul , Luca Benini , Marian Verhelst
show 1 more author
Tobias Grosser
This is my paper · ORCID
classification cs.PL
keywords compilerbackendstaticsingleassignmentRISC-VISAextensionsmicro-kernelsregisterallocationFPUutilizationstreamingregisters
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to show that the classic hourglass compiler design, where one low-level IR feeds a generic backend, is not the only viable route to high performance on specialized hardware. The authors instead build a backend as a stack of structured SSA-based IRs that carry domain knowledge about a RISC-V accelerator's custom extensions, namely hardware loops and streaming registers, all the way down to assembly. Lowering automatically from a high-level linear algebra DSL, their prototype reports up to 90% FPU utilization on representative deep-learning kernels, and up to 95% when kernels are written directly in the backend's low-level dialects. If this holds, domain-specific compilation could reach custom accelerators without expert-tuned assembly or library code, which is what the paper aims to establish.

What carries the argument

The load-bearing machinery is a family of SSA-based IRs arranged by abstraction level: a low-level RISC-V dialect whose operations are assembly instructions, structured control-flow dialects that keep loops and function calls with region bodies, and target-specific dialects that model streaming registers, stream configurations as compile-time constants, and hardware loops as operations with explicit iteration counts and region bodies. The central transformation is progressive lowering: a high-level generic operation is first rewritten into a memory-stream operation with explicit iteration bounds, then into a streaming region that wraps hardware-loop operations, so access patterns and loop control are decided while domain structure still exists. Register allocation walks the structured regions backwards in three passes, allocating loop-carried values first so the same physical register is reused across iterations, and never spills. Scheduling uses unroll-and-jam with an unroll factor of at least four to hide the target FPU's three-stage pipeline.

What would settle it

Modify the cycle-accurate RTL simulator so that floating-point multiply and add have different pipeline latencies, say five and three cycles, while keeping the generated schedule and unroll factor fixed at four; if FPU utilization drops substantially below the reported 90-95%, the uniform three-stage assumption is load-bearing. Alternatively, sweep the unroll factor from one to eight on the same kernels and check that the utilization plateau starts at four as claimed.

Watch

Extended reading notes

Core claim

The paper's central claim is that a multi-level backend, composed of several structured SSA IRs rather than a single catch-all low-level representation, can generate near-peak micro-kernels for an accelerator with non-standard ISA extensions. Concretely, the authors encode RISC-V assembly as SSA operations, add higher-level dialects that model the accelerator's streaming registers and hardware repetition loops, and perform register allocation over structured regions in three linear passes instead of reconstructing liveness from unstructured control flow. With progressive lowering from a high-level linear algebra abstraction through a memory-stream representation, compiler-generated kernels reach 90% FPU utilization on representative ML kernels, while kernels expressed directly in the low-level dialects reach up to 95%. The same kernels compiled through a conventional general-purpose compiler flow peak near 42% utilization, which the paper attributes to the information loss caused by lowering into a single low-level IR.

Load-bearing premise

The automatic scheduler assumes every floating-point operation on the target takes exactly three pipeline stages, so unrolling the inner loop by at least four eliminates all read-after-write stalls; if FPU latencies differ by operation or the memory system adds variable delays, the reported 90-95% utilization would drop.

Editorial extensions

If this is right

  • Custom RISC-V ISA extensions such as hardware loops and streaming registers can be targeted automatically from a high-level DSL, removing the need to hand-write assembly for each kernel.
  • Backends organized as several structured IRs can keep domain information available for scheduling, register allocation, and code generation instead of discarding it at a single mid-level IR.
  • Spill-free register allocation over structured regions is sufficient for high-performance linear algebra micro-kernels, so general-purpose spilling heuristics need not be part of micro-kernel compilation.
  • Kernel performance approaches the roofline as problem size grows, meaning accelerator setup and function-call overheads dominate only on small inputs.
  • Existing general-purpose compiler flows leave roughly half of FPU capacity unused on this accelerator, and the multi-level backend closes most of that gap.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A fair head-to-head test would require a competing backend that also understands the target extensions; the paper presents its general-purpose compilation flows as context rather than as direct baselines, so the 42% figure is indicative, not a controlled comparison.
  • The same multi-level recipe should transfer to other accelerators whose custom features can be expressed as structured SSA operations, but the paper demonstrates only one target; implementing a second backend would test the claim's generality.
  • The fixed rule of unrolling by at least the pipeline depth suggests a generic scheduling heuristic; for targets with non-uniform FPU latencies or variable memory delays, the compiler would need a latency model or autotuning.
  • Because structured control flow is a precondition for the spill-free allocator, applying this backend to general-purpose code would require reintroducing liveness analysis and spilling; the paper explicitly scopes itself to linear algebra micro-kernels.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper proposes a compiler backend architecture built from multiple structured SSA-based IRs rather than a single low-level IR, and implements it for the Snitch RISC-V core with its SSR/FREP ISA extensions. The authors introduce a family of MLIR/xDSL dialects (rv, rv_cf, rv_scf, rv_func, rv_snitch, snitch_stream, memref_stream), a spill-free register allocator that exploits structured control flow, and a progressive lowering path from linalg to Snitch assembly. The evaluation uses a cycle-accurate Verilator model and reports up to 95% FPU utilization for handwritten micro-kernels and up to 90% for kernels generated from a high-level linalg DSL, with a step-by-step ablation for the MatMul kernel.

Significance. If the results are reproducible, this is a valuable demonstration that a multi-level, structured backend can target custom ISA extensions without hand-written assembly. The artifact is a notable strength: it pins tool versions and a commit hash, uses deterministic cycle-accurate simulation, and provides a full Docker-based reproduction workflow. The ablation in Table 3 cleanly separates the effects of streams, scalar replacement, FREP, fusion, and unroll-and-jam, and the register-allocation study covers a reasonable kernel set. The main gaps are the lack of direct evidence for the scheduler's unroll-factor heuristic, and the fact that the Clang/MLIR comparison flows do not target Snitch's custom extensions, so they are not equal-footing baselines.

major comments (2)
  1. [Section 3.4, Table 3] The claim that stalls are minimized when the unroll factor is at least four rests on an unstated and unverified hardware assumption: that every Snitch FPU operation has a three-stage pipeline with issue-to-use latency of at most three cycles. No citation, Verilator latency measurement, or unroll-factor sweep is provided. Since Table 3 shows that Unroll-and-Jam is the single step that raises MatMul occupancy from 24.5% to 90.67%, this assumption is load-bearing for the headline result. Please add a concrete reference to the Snitch specification or a direct measurement of FPU latency, and ideally a small sweep (e.g., unroll factors 2, 3, 4, 5, 6) on the MatMul kernel to demonstrate that the chosen factor is sufficient and that the scheduler is not overfit to the specific N=5 shape. Also reconcile the statement in Section 4.4 that kernels 'process four reductions at a time' with Table 3's 'five elements' interleaving.
  2. [Section 4.1, Section 4.4, Figure 10] The paper correctly states that the Clang and MLIR flows are 'not a baseline for direct comparison' because they do not target the Snitch ISA extensions, but it then uses the large utilization gap in Figure 10 to support the conclusion that the LLVM backend is the limiting factor. Because those flows cannot issue SSR or FREP instructions, the gap could be attributed entirely to the absence of custom-extension support rather than to the multi-level IR structure. The paper should either remove the comparative language, clearly label the plots as reference points rather than baselines, or add a variant that targets the same custom instructions from a flat low-level IR so that the contribution of the multi-level structure is not conflated with the contribution of the extensions.
minor comments (5)
  1. [Section 4.4, Figure 10 caption] The text in Section 4.4 says the high-level pipeline reaches 'as high as 90%' FPU utilization, while the Figure 10 caption says kernels 'reach up to 95% FPU utilization'; clarify which pipeline produced the 95% figure (the handwritten low-level path in Section 4.2 or the high-level path).
  2. [Section 4.2] The paper states that the FPU peak is two FLOPs per cycle for 64-bit FMA operations, but the MatMulT kernel on 32-bit data is reported at 2.45 FLOPs/cycle; explain the 32-bit packed-SIMD peak so the throughput number is placed in context.
  3. [Table 3] The 'FRep' column header is not defined in the caption; state explicitly whether the entry is the number of emitted FREP instructions.
  4. [Artifact Appendix A.2] The artifact appendix lists xDSL 0.23.01 while Section 4.1 states xDSL v0.21.1; align the versions or explain the discrepancy.
  5. [Figure 9] The labels such as 'MatMulT 1xK 40xK' are hard to parse; consider separating the shape annotations into a legend or subcaptions for readability.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the headline FPU-utilization numbers are measured against an external RTL simulator and a roofline, and the unroll factor is chosen from a stated pipeline-depth assumption rather than fitted to the reported results.

full rationale

The paper's central claim is an engineering measurement, not a derivation: FPU utilization is computed from cycle counts obtained on a Verilator cycle-accurate RTL simulation of Snitch, against a theoretical roofline derived from FLOP counts and peak FP throughput (Section 4.1). The scheduler selects an unroll factor from a stated hardware property ('For Snitch, the FPU has three stages for all operations, so stalls are minimized when the unroll factor is at least four', Section 3.4) rather than fitting the factor to the measured 90.67% occupancy in Table 3; the row for Unroll-and-Jam reports a measured outcome, not a fitted prediction. No equations in the paper equate the target result to an input, and no benchmark constant is fit and then renamed as a prediction. The self-citations present (Snitch [80], Stream Semantic Registers [65], xDSL [14,31]) describe external hardware and tooling that are re-derived or executed in the artifact: the open-source Snitch SystemVerilog is compiled with Verilator, and the artifact is archived at 10.5281/zenodo.14052014. None of these self-citations is loaded with a uniqueness theorem or an unverified premise that forces the paper's conclusion. The 'spill-free' claim is explicitly scoped to kernels with spare registers (Table 2), and the paper states this choice 'might become a concern for those with more involved features such as deeper loop nests', which is a stated limitation rather than a circular step. The main vulnerability, the unverified three-stage FPU latency assumption, is a correctness risk that would lower utilization if wrong, not a circularity. Overall, the evaluation is self-contained against an external simulator and roofline, so no circularity is found.

Assumptions & free parameters 1 free parameters · 4 assumptions · 1 invented entities

The paper's results rest on standard SSA/MLIR theory, documented Snitch hardware behavior (pipeline, FREP, SSRs, TCDM), and three hand-set design choices: an unroll factor of at least four, a register pool limited to caller-saved registers, and a no-spilling policy. No constants are fitted to benchmark data; the unroll factor is selected from the stated pipeline depth. The multi-level IRs are the only newly introduced artifacts, and they are backed by released code.

free parameters (1)
  • Unroll factor for unroll-and-jam = at least 4 (5 for MatMul inner loop)
    Chosen by hand from the stated 3-stage FPU pipeline depth, not swept or autotuned; performance figures depend on it.
assumptions (4)
  • standard math SSA form guarantees that a linear walk of use-def chains respects definition order, extended to MLIR regions with blocks and arguments.
    Invoked in Section 3.3 to justify a single backward-walk register allocation; it is a standard result of SSA IR design, not proved here.
  • domain assumption Every Snitch FPU operation has a three-stage pipeline, so unrolling by at least four removes RAW stalls.
    Stated in Section 3.4 and used to select the unroll factor; the paper does not measure per-operation latencies.
  • domain assumption Snitch's in-order core and software-managed TCDM make performance predictable, so a simple schedule suffices without exploring a schedule space.
    Stated in Section 3.4; it justifies skipping autotuning and is a property of the specific hardware, not a general result.
  • ad hoc to paper Register spilling is undesirable for micro-kernels, so a spill-free allocator is the right target.
    Positioned in Section 3.3 as the design stance; it shapes both the allocator and the evaluation, and is a reasonable but not proven premise.
invented entities (1)
  • New xDSL/MLIR dialects for RISC-V and Snitch (rv, rv_cf, rv_scf, rv_func, rv_snitch, snitch_stream, memref_stream) independent evidence
    purpose: Represent assembly instructions, structured control flow, ABI conventions, streaming registers, FREP loops, and high-level stream abstractions in SSA form for progressive lowering.
    These are software abstractions, not speculative physical entities; they are implemented and shipped in the artifact (Zenodo DOI, commit 902bfbc8), and the paper shows generated IR and assembly, giving a concrete falsifiable handle.

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Cite this review

Pith. "Pith review of A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions." pith.science (2026). https://pith.science/paper/S7LOMCDF

@misc{pith2026250204063,
  author       = {Pith},
  title        = {Pith review of: A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/S7LOMCDF}},
  note         = {Machine review of arXiv:2502.04063}
}
read the original abstract

High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offered by numerous compilers (e.g., MLIR, TVM, OpenXLA), performance-critical micro-kernels are left to specialized code generators or handwritten assembly. Even though widely-adopted compilers (e.g., LLVM, GCC) offer tuned backends, their CPU-focused input abstraction, unstructured IR, and general-purpose best-effort design inhibit tailored code generation for innovative hardware. We think it is time to widen the classical hourglass backend and embrace progressive lowering across a diverse set of structured abstractions to bring domain-specific code generation to compiler backends. We demonstrate this concept by implementing a custom backend for a RISC-V-based accelerator with hardware loops and streaming registers, leveraging knowledge about the hardware at levels of abstraction that match its custom ISA. We use incremental register allocation over structured IRs, while dropping classical spilling heuristics, and show up to 90% FPU utilization across key DNN kernels. By breaking the backend hourglass model, we reopen the path from domain-specific abstractions to specialized hardware.

Figures

Figures reproduced from arXiv: 2502.04063 by the authors.

Figure 1
Figure 1. Traditional backends offer a narrow interface to abstraction-rich frameworks like MLIR, often triggering the development of expert-tuned libraries to exploit custom ac￾celerator features (left). Our multi-level backend combines target-specific abstractions with progressive lowering offer￾ing a wide backend for accelerator code generation (right). a result, C/C++, Fortran, Swift, Rust, and many more lan￾guages that t… view at source ↗
Figure 2
Figure 2. Organizing program abstractions as SSA-based IRs enables a modular approach for compiler construction. The above vector-matrix product in MLIR makes the use-def rela￾tionships explicit and obviates the need for intricate analyses by capturing information at the right abstraction level (e.g., directly expressing iteration types in linalg.generic). name, and each use of a value refers to a unique definition. We use SS… view at source ↗
Figure 3
Figure 3. Simplified high-level overview of the Snitch micro￾architecture used in our evaluation (Section 4) based on [80]. FPU utilization can be maximized using hardware loops (FREP) to remove explicit loop control flow and SSRs to eliminate explicit FP load/stores for affine access patterns. 2.2 Machine Learning Abstractions in SSA SSA is well-suited in expressing programs with IRs at differ￾ent abstraction levels for opti… view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: Our multi-level compiler backend utilizes a host of MLIR dialects to generate efficient code, tailored to the RISC-V Snitch accelerator. The high-level information from the linalg dialect is progressively lowered to the custom Snitch ISA extensions. Our modular approac…
Figure 6
Figure 6. Figure 6: Our multi-level backend uses a mix of SSA-based IRs to represent different levels of abstraction around the RISC-V ISA for a matrix-vector calculation. The SSA formulation of the ISA empowers the compiler to employ well-understood analyses and transformations and, when…
Figure 7
Figure 7. Figure 7: The memref_stream abstractions bridge the gap between high-level linear algebra abstractions and Snitch accelerator capabilities, allowing us to schedule computation before separating access from execution. a feature required for general-purpose register allocation, ha…
Figure 8
Figure 8. Figure 8: We compare our prototype compiler with flows using Clang and MLIR, and separately evaluate the expres￾sivity of our MLIR backend (Section 4.1). (Section 2.4). We compile the open-source reference Sys￾temVerilog implementation of Snitch with Verilator [13] to generate t…
Figure 9
Figure 9. Figure 9: Our low-level representation is flexible enough to represent linear algebra operations commonly used in machine learning (ML) reaching high FPU utilization, reaching 95% peak FPU utilization and 94% of theoretical maximum throughput. Despite the high FPU utilization, t…
Figure 10
Figure 10. Figure 10: Selected micro-kernels compiled with our end-to-end prototype compiler reach up to 95% FPU utilization. In contrast, MLIR does not outperform a naive C implementation compiled with Clang on this platform. 4 12 20 28 36 44 52 60 N 4 12 20 28 36 44 52 60 K 22 25 34 35 4…
Figure 11
Figure 11. Figure 11: Sustained throughput of the 64-bit MatMul kernel (𝐶𝑀×𝑁 = 𝐴𝑀×𝐾𝐵𝐾×𝑁 when 𝑀 = 1). We achieve throughput of over 90% (≥ 1.80 FLOPs/cycle) of the theoretical peak (above the white border) as shape sizes increase, indicating that the computation offsets constant overheads. …

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Pith tools

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