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Paper Citation Record · LEDGER

AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 8 inbound Pith citation observations for arXiv:2503.19174.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2503.19174 v2

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 8 of 8 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 8 of 8 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-06T22:55:09.374587Z

measured 1 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

0
arxiv_reference, observed 2026-08-05T02:28:24.338817Z

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 608bd155-9046-40f0-9577-3b621ecabda7 · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 77

Resolution
unresolved
no resolver link, observed 2026-08-06T22:55:09.374587Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T22:55:09.374587Z digest=sha256:ca38854dc3840c0a17c81b8928ecd1005a1c5a516eea6a853aa64eabfe444b11

Observation 59bced4d-db67-4476-849e-3213eb2b07ce · inbound

AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction cites this paper.

AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 18

Resolution
unresolved
no resolver link, observed 2026-08-06T17:37:24.909810Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T17:37:24.909810Z digest=sha256:c8b634977c843dfec5f914fe87f53cfd5b1014087ab24092bd010d45bb33fde2

Observation cdb40787-ac25-4648-b9ad-3f4a0e7101b3 · inbound

CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations cites this paper.

CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 6

Resolution
verified exact
arxiv_id, observed 2026-05-11T00:05:50.945541Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-05-10T18:41:42.906023Z digest=sha256:139b9ea1ef4dc1fd9418e255d5988a8c4f42c6655b164807173d3c6dc6f990c2

Observation 3c1339f1-3b63-41cc-a030-0b14269fdd83 · inbound

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation cites this paper.

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 7

Resolution
verified exact
arxiv_id, observed 2026-05-11T06:46:50.586768Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-05-10T17:26:47.139265Z digest=sha256:6c2eda77e368be931140463b59ffb86afc9889fd0c8e0e3cad8e9b3970bd933c

Observation a4c618c5-0a8d-44e4-8b01-eeed9cef2849 · inbound

Autoformalizing Memory Specifications with Agents cites this paper.

Autoformalizing Memory Specifications with Agents AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 25

Resolution
verified exact
arxiv_id, observed 2026-05-09T20:47:37.160614Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=arxiv_source observed=2026-05-09T20:43:27.934095Z digest=sha256:7f27f0b1bdd9d4bfd50857b3f21c7f77ee9eaa046f7543c2d69a3ececb282f9b

Observation a6576e5b-5edd-4823-81b5-588cfbaffec1 · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 4

Resolution
verified exact
arxiv_id, observed 2026-07-03T00:47:30.467132Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-06-27T17:01:24.292776Z digest=sha256:9eb69dc444747fc11883597f2e59f7c2e1f913328b419fee0604c567d5a1f036

Observation bbf92405-5712-46f3-9b06-2d9f2b9616cf · inbound

Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification cites this paper.

Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 3

Resolution
verified exact
arxiv_id, observed 2026-07-04T07:49:38.662172Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-06-26T12:52:27.936359Z digest=sha256:df5c81d0e49ef6455ea75d7ab7f428c5fc69e0791c926e9911ca73dc4ae88fed

Observation 314b0802-6e66-4314-a583-6e73cd9d0468 · inbound

Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification cites this paper.

Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

Reference 4

Resolution
metadata mismatch
arxiv_id, observed 2026-06-26T12:59:29.731629Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-06-26T12:52:27.936359Z digest=sha256:8dc5561bdaac7c3fe838b23546404534423d2a4cb67cca02f281a59ef4541d62