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TileLink: Generating Efficient Compute-Communication Overlapping Kernels using Tile-Centric Primitives

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arxiv 2503.20313 v3 pith:EPC2SP3D submitted 2025-03-26 cs.DC

classification cs.DC
keywords tilelinkcommunicationkernelsoverlappingperformancecomputationefficientoperators
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

Large deep learning models have achieved state-of-the-art performance in a wide range of tasks. These models often necessitate distributed systems for efficient training and inference. The fundamental building blocks for distributed model execution are intra-layer parallel operators. The most effective approach to enhancing the performance of intra-layer parallel operators involves overlapping computation with communication. The overlapping can be achieved through either operator decomposition or kernel fusion. While decomposing operators is straightforward to implement, it often results in suboptimal performance. On the other hand, fusing communication kernels with compute kernels demands significant expertise and is error-prone. In this paper, we propose TileLink to enable efficient compilation and generation of overlapped compute-communication kernels. TileLink is composed of frontend and backend. In the frontend, TileLink decouples the design space of communication and computation, linking these two parts via tile-centric primitives. In the backend, TileLink translates these primitives into low-level communication instructions, integrating the communication and computation components to achieve overlapped execution. In experiments, TileLink achieves from $1.17\times$ to $20.76\times$ speedup to non-overlapping baseline and achieves performance comparable to state-of-the-art overlapping libraries on GPUs.

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Forward citations

Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters

    cs.DC 2026-07 conditional novelty 7.0 of 10

    A tile-centric analytical model predicts GPU kernel latency and cache behavior purely from microbenchmark-calibrated hardware rates, reaching about 12% GEMM error and 13% end-to-end LLM serving error across five GPU lines.

  2. Characterizing Real-World Bugs in Tile Programs for Automated Bug Detection

    cs.SE 2026-05 unverdicted novelty 7.0 of 10

    A taxonomy of 301 real tile-program codegen bugs: 48.8% are type/operator bugs, 19.3% are memory bugs, and detection needs shape-aware fuzzing plus differential oracles.

  3. Syncopate: Efficient Multi-GPU AI Kernels via Automatic Chunk-Centric Compute-Communication Overlap

    cs.DC 2026-01 unverdicted novelty 7.0 of 10

    Syncopate automatically overlaps compute and communication at fine chunk granularity inside a single fused Triton kernel, yielding 1.3x average and up to 4.7x end-to-end speedup on multi-GPU workloads.

  4. SiFAR: Synchronization-Free All-Reduce for Low-Latency LLM Inference

    cs.DC 2026-07 accept novelty 6.5 of 10

    SiFAR cuts All-Reduce latency up to 52% and end-to-end decode throughput up to 18.6% at TP=8 by dual buffering, in-switch redundant pull, and speculative reduction with validation.

  5. Robix: A Unified Model for Robot Interaction, Reasoning and Planning

    cs.AI 2025-09 conditional novelty 6.0 of 10

    A three-stage-trained VLM unifies robot planning and dialogue, and beats commercial VLMs on the authors' interactive-task benchmarks.

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