Paper Citation Record · LEDGER

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model

As of 16 August 2026, this Paper Citation Record lists 39 of 39 outbound references and 1 inbound Pith citation observation for arXiv:2504.14560.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2504.14560 v3

Coverage vector

measured 39 of 39 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-16T11:50:20.420989Z

measured 40 of 40 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-16T06:30:59.297886+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-07-30T20:17:57.534211Z

measured 1 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-05T02:28:24.338817Z

Reference resolution

39 of 39 outbound references displayed

verified exact1
verified fuzzy9
unresolved29
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

0
pith, observed 2026-08-05T02:28:24.338817Z

Outbound references

Observation 25c1e1f3-7463-4626-a4be-b9a1e3660db8 · outbound

This paper cites Chip-chat: Chal- lenges and opportunities in conversational hardware design,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Chip-chat: Chal- lenges and opportunities in conversational hardware design,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:21.091156Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 93b744e2-9ba2-4c5d-bb3e-e3bd4007d919 · outbound

This paper cites AIvril: AI-Driven RTL Generation With Verification In-The-Loop.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model AIvril: AI-Driven RTL Generation With Verification In-The-Loop

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.249038Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bedd8c37-4925-4033-b591-1ee5f527b4ab · outbound

This paper cites OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.254819Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f5d92ea3-d9a6-46a6-a8ee-5696bf73d7af · outbound

This paper cites Verigen: A large language model for verilog code generation,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Verigen: A large language model for verilog code generation,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.259969Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9511668c-8b5a-4df7-94ab-6c86610bd5d4 · outbound

This paper cites Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.265708Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 34571710-e292-4ac7-a1aa-d73c7006cce6 · outbound

This paper cites VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.269954Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation afd4fafc-e2a8-4c57-b21c-06e55c9d6bca · outbound

This paper cites EDA-Aware RTL Generation with Large Language Models.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model EDA-Aware RTL Generation with Large Language Models

Reference 7

Resolution: verified exact; local_arxiv, observed 2026-08-16T11:50:20.826256Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 5346da6a-7879-4e40-8b85-b51586c31308 · outbound

This paper cites Evaluating Large Language Models Trained on Code.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Evaluating Large Language Models Trained on Code

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.279580Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fd5b1a0d-d959-4f5c-94bf-6409c37032ea · outbound

This paper cites Autovcoder: A systematic framework for automated verilog code gen- eration using llms,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Autovcoder: A systematic framework for automated verilog code gen- eration using llms,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:21.059935Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation db7426c3-99a7-4939-9161-511c05fef613 · outbound

This paper cites Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.287755Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 37aed44d-7218-400b-a03c-2d322942adb2 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Verilogeval: Evaluating large language models for verilog code generation,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.291741Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2b7aa8f4-21d2-4cbe-8fe0-0733b536c374 · outbound

This paper cites Rtllm: An open-source benchmark for design rtl generation with large language model,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Rtllm: An open-source benchmark for design rtl generation with large language model,

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.295970Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e8f3cda1-ef85-4f85-984f-b9bb05b583cd · outbound

This paper cites Rtl-repo: A benchmark for evaluating llms on large-scale rtl design projects,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Rtl-repo: A benchmark for evaluating llms on large-scale rtl design projects,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.300000Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 643fc5d6-6ad0-4d12-93e3-619486da120e · outbound

This paper cites BetterV: Controlled Verilog Generation with Discriminative Guidance.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.304136Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 159f1594-bdb5-4bf3-86e4-5cc13f546e29 · outbound

This paper cites OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.307922Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 13184d1c-b475-44f0-9580-ca6ed251f522 · outbound

This paper cites Pyranet: A multi-layered hierarchical dataset for verilog,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Pyranet: A multi-layered hierarchical dataset for verilog,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.312286Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a18bd97a-6293-4af4-8ba4-6d0c9c101575 · outbound

This paper cites Mg-verilog: Multi- grained dataset towards enhanced llm-assisted verilog generation,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Mg-verilog: Multi- grained dataset towards enhanced llm-assisted verilog generation,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.317414Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3fbbbfda-276f-4ef0-8e81-d7e34b71a737 · outbound

This paper cites CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.321110Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5ede9dae-3a78-46e4-a16b-f262cebcab42 · outbound

This paper cites Open ai codex: An inevitable future?.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Open ai codex: An inevitable future?

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.988637Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 67f1a666-5610-48bc-8e5e-c6179f52a56a · outbound

This paper cites Towards the imagenets of ml4eda,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Towards the imagenets of ml4eda,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.974782Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation cc73cbe5-c129-4d64-8d68-f12decf5a188 · outbound

This paper cites Revisiting verilogeval: A year of improvements in large-language models for hardware code generation,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Revisiting verilogeval: A year of improvements in large-language models for hardware code generation,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.959132Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 08eb6c26-3dfe-4151-81d6-044ade77544b · outbound

This paper cites HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.337294Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e476a592-8189-481a-8d2d-6ac14877ea85 · outbound

This paper cites VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.342729Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e9c2fb50-f3de-427e-bdb2-df9ed34db234 · outbound

This paper cites Paradigm-Based Automatic HDL Code Generation Using LLMs.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Paradigm-Based Automatic HDL Code Generation Using LLMs

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.348089Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bda3d89b-a9ea-49c5-9bf0-500d53130b0e · outbound

This paper cites Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.353248Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7c421bd2-41ec-43b9-8d43-e17cc4f96543 · outbound

This paper cites KodCode: A Diverse, Challenging, and Verifiable Synthetic Dataset for Coding.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model KodCode: A Diverse, Challenging, and Verifiable Synthetic Dataset for Coding

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.358097Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6b562422-77ea-481d-82c8-a52d6a42dd7b · outbound

This paper cites Synopsys design compiler,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Synopsys design compiler,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.944321Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 6dff6704-530d-48b5-a799-4b8e374386db · outbound

This paper cites A Comparative Study on Reasoning Patterns of OpenAI's o1 Model.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model A Comparative Study on Reasoning Patterns of OpenAI's o1 Model

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.369104Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 95115917-4b29-4c12-b7e5-a55c66a696ae · outbound

This paper cites Stop Overthinking: A Survey on Efficient Reasoning for Large Language Models.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Stop Overthinking: A Survey on Efficient Reasoning for Large Language Models

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.373796Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 99723143-1dff-4931-90d4-e0e0e6350784 · outbound

This paper cites A survey of efficient reasoning for large reasoning models: Language, multimodality, and beyond,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model A survey of efficient reasoning for large reasoning models: Language, multimodality, and beyond,

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.379392Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 105f9403-c128-4b3f-8d80-55ef27d3e93b · outbound

This paper cites Dynamic LLM Routing and Selection based on User Preferences: Balancing Performance, Cost, and Ethics.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Dynamic LLM Routing and Selection based on User Preferences: Balancing Performance, Cost, and Ethics

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.384413Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0bc31748-6ccf-4d0b-895c-f4c8aeda23aa · outbound

This paper cites DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.390047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c5dee153-1192-46e5-9066-6749c29e90eb · outbound

This paper cites s1: Simple test-time scaling.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model s1: Simple test-time scaling

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.395323Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ba8ba5c9-61f1-4478-ad90-d4ae57c6feb1 · outbound

This paper cites Icarus verilog: open-source verilog more than a year later,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Icarus verilog: open-source verilog more than a year later,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.930288Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 89ac80c4-fd4a-4e8d-921b-259fcc3c62be · outbound

This paper cites Qwen Technical Report.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Qwen Technical Report

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.404453Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6dc46ec7-6e0e-4ffe-8984-50467bf4427d · outbound

This paper cites Lora: Low-rank adaptation of large language models,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Lora: Low-rank adaptation of large language models,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.915790Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 343ccad9-efaf-4819-89ee-327f6a38694b · outbound

This paper cites Introducing pytorch fully sharded data parallel (fsdp) api,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Introducing pytorch fully sharded data parallel (fsdp) api,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T11:50:20.901523Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation a2a8e360-32a6-4c0d-b59e-582870e7cdbf · outbound

This paper cites Decoupled weight decay regularization,.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Decoupled weight decay regularization,

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.417009Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ef7c5ab6-9dff-45f2-af5a-727e062bc151 · outbound

This paper cites Decoupled Weight Decay Regularization.

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Decoupled Weight Decay Regularization

Reference 2019

Resolution: unresolved; no resolver link, observed 2026-08-16T11:50:20.420989Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

Observation ab264b57-c66b-48a5-9a84-c052cb2bdc36 · inbound

CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation cites this paper.

CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model

Reference 15

Resolution: verified exact; local_arxiv, observed 2026-07-30T20:20:56.685455Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.