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HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL

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arxiv 2503.16528 v1 pith:GICFZRUV submitted 2025-03-18 cs.CL cs.AI

classification cs.CLcs.AI
keywords generationllmscapabilitiesframeworkhallucinationshdlcorecodeimproving
verification ladder T0 review T1 audit T2 compute T3 formal
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Recent advances in large language models (LLMs) have demonstrated remarkable capabilities in code generation tasks. However, when applied to hardware description languages (HDL), these models exhibit significant limitations due to data scarcity, resulting in hallucinations and incorrect code generation. To address these challenges, we propose HDLCoRe, a training-free framework that enhances LLMs' HDL generation capabilities through prompt engineering techniques and retrieval-augmented generation (RAG). Our approach consists of two main components: (1) an HDL-aware Chain-of-Thought (CoT) prompting technique with self-verification that classifies tasks by complexity and type, incorporates domain-specific knowledge, and guides LLMs through step-by-step self-simulation for error correction; and (2) a two-stage heterogeneous RAG system that addresses formatting inconsistencies through key component extraction and efficiently retrieves relevant HDL examples through sequential filtering and re-ranking. HDLCoRe eliminates the need for model fine-tuning while substantially improving LLMs' HDL generation capabilities. Experimental results demonstrate that our framework achieves superior performance on the RTLLM2.0 benchmark, significantly reducing hallucinations and improving both syntactic and functional correctness.

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  1. A Progressive Approach to Synthesizable RTL Design Generation Using LLMs

    cs.AR 2026-07 conditional novelty 6.0 of 10

    VeriRefine boosts LLM-generated RTL correctness to 94.0% on RTLLM v2.0 and 98.1% on VerilogEval-Human v2 by refining and auditing a per-signal intermediate representation before code generation.

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