REVIEW 2 major objections 4 minor 1 references
Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates
T0 review · 2 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash
Pith's one-line read The paper reports that hybrid pulsed laser deposition grows crystalline, out-of-plane textured zinc sulfide films on amorphous and polycrystalline back-end-of-line-compatible substrates at 400 °C, and electrical measurements indicate the…
desk verdict Solid growth study undermined by an electrical interpretation that reads too much into a flat C-V curve; the structural data are worth a careful referee. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing mechanism is hybrid pulsed laser deposition (hPLD): a 248 nm KrF laser ablates a dense ZnS target while tert-butyl disulfide vapor is metered into the chamber without a carrier gas, providing a sulfur-rich environment that compensates for sulfur loss at elevated temperature. This is what enables crystalline, textured growth at 400 °C on surfaces with no epitaxial relation to ZnS. Structural characterization relies on powder XRD for out-of-plane texture, GIWAXS for in-plane ordering, and X-ray reflectivity and atomic force microscopy for smoothness; electrical characterization uses J-V and MOSCAP measurements, with the flat capacitance treated as evidence of a nearly intrinsic, defect-poor film.
What would settle it
Measure the same MOSCAPs' capacitance from 1 kHz to 1 MHz and under illumination, or fabricate a field-effect transistor and attempt to gate-modulate the channel; if the flat C-V shows strong frequency dispersion, or if a transistor shows no channel modulation, then the flat curve is a contact or depletion artifact rather than proof of an intrinsic, low-defect film.
Extended reading notes
Core claim
The central discovery is that the hybrid PLD process produces wurtzite ZnS with a consistent c-axis (00l) out-of-plane texture on all substrates, including amorphous oxides and nitrides, with no requirement for lattice matching; in-plane grain orientation remains random except on yttrium oxide, where the template's own texture imposes partial ordering. On the electrical side, metal-insulator-metal and MOSCAP structures show leakage near $10^{-5}\ \mathrm{A\,cm^{-2}}$ at $0.40\ \mathrm{MV\,cm^{-1}}$ and a nearly flat C-V curve, which the paper reads as ZnS and SiO2 acting as two capacitors in series, with ZnS behaving as a highly intrinsic semiconductor. The implication is that unintentional doping is low, so any future p-type behavior will come from deliberate dopants rather than from background defects.
Load-bearing premise
The paper's suggestion that ZnS is highly intrinsic rests on interpreting a flat capacitance-voltage curve as the signature of a nearly defect-free insulating layer; if that flatness instead comes from full depletion, blocking contacts, or interface and series-resistance effects, the low-defect conclusion does not follow.
Editorial extensions
If this is right
- If hPLD grows textured, smooth ZnS on every surface tested at 400 °C, the recipe can be transferred directly to a back-end stack without changing the dielectrics or metals already present.
- If undoped ZnS is as intrinsic as the flat C-V suggests, then copper or nitrogen doping should yield p-type conductivity without being swamped by background donors.
- Leakage near $10^{-5}\ \mathrm{A\,cm^{-2}}$ at $0.40\ \mathrm{MV\,cm^{-1}}$ indicates the films can hold the fields needed for a transistor channel without excessive off-state current.
- Because in-plane order is only imposed by the yttrium oxide template, films on the other substrates should show grain-boundary-dominated transport, and Y2O3 offers a control surface to test that.
Reading between the lines
- If the intrinsic interpretation holds, a systematic copper-doping series in the same chamber is the immediate next experiment; a monotonic rise in hole concentration with copper fraction would confirm both the baseline and the dopability.
- The absence of Hall and frequency-dependent data leaves room for an alternative reading of the flat C-V, so a dedicated Hall or Mott-Schottky study would settle whether the low-defect claim is quantitative.
- Comparing ZnS on textured Y2O3 with ZnS on amorphous SiNx could separate texture effects from grain-boundary conduction, since both are smooth but only the former has in-plane ordering.
- The same hPLD sulfur-precursor strategy may extend to other vapor-pressure-mismatched sulfides, making textured low-temperature growth a general route rather than a ZnS-specific result.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper reports growth of zinc sulfide (ZnS) thin films by hybrid pulsed laser deposition (hPLD) at 400°C on a variety of amorphous and polycrystalline BEOL-compatible substrates: SiNx, thermal SiO2, Y2O3, HfO2, sapphire, Pt, and TiN. Structural characterization by θ-2θ XRD shows 'weak out-of-plane texture' (00l reflections) on all surfaces; GIWAXS shows random in-plane orientation on most surfaces but some ordering on Y2O3; XRR and AFM indicate smooth films. Electrical characterization consists of J-V measurements on a ZnS/Pt stack and C-V measurements on ZnS/SiO2 MOSCAPs. The flat C-V curve is interpreted as evidence that ZnS is 'highly intrinsic with very low unintentional, electrically active point defects,' motivating future p-type doping studies.
Significance. If the electrical claim were well supported, the work would be a useful step toward a p-type channel material for BEOL-compatible 3D integration, because it demonstrates 400°C growth of textured, smooth ZnS on multiple substrates and reports a bilayer-capacitor response. The structural results appear solid: the XRD, GIWAXS, XRR, and AFM data are internally consistent, and the hPLD method has been previously published, so the growth portion is reproducible and credible. However, the central electrical conclusion—that flat C-V implies a nearly defect-free, highly intrinsic semiconductor—is not uniquely supported by the presented data, and this conclusion is what motivates the proposed p-type doping program. The paper also provides honest statements of limitations (e.g., 'cautious inference' about interface trapping, need for future FET measurements), which is commendable.
major comments (2)
- [III.D, Fig. 4(a)] The flat C-V curve is not uniquely diagnostic of a 'highly intrinsic' ZnS film. A flat capacitance that is independent of bias also results if the semiconductor is fully depleted over the entire voltage range (which can occur even for moderately doped films when the maximum depletion width exceeds the film thickness), if the top contact is blocking, if interface states pin the surface potential, or if series resistance dominates the measurement. The authors themselves report ε_ZnS = 5.6, below the bulk value of 8, and attribute this to 'interface trapping effects' (Section III.D), indicating that non-idealities already affect the measured capacitance. Without Hall-effect measurements, frequency-dependent C-V, or a transistor transfer characteristic, the data cannot distinguish a nearly defect-free semiconductor from a fully depleted or contact-limited film. Because the 'highly intrinsic' conclusion is the paper's central electrical claim and the stated motivation for future p-type doping studies, this underdetermination is load-bearing and must be addressed.
- [III.D, Fig. 4 and Fig. S8] The electrical data are presented without error bars, statistics over devices, or measurement details such as the number of devices tested and the spread in extracted dielectric constants. The J-V data are shown for a single ZnS/Pt stack (Fig. S8) and for the MOSCAP (Fig. 4(b)), but no breakdown field, comparison to a control sample, or temperature dependence is given to support the claim that the leakage current is 'low.' Reporting device-to-device variability and at least one independent electrical probe (e.g., Hall effect or capacitance-frequency sweep) would substantially strengthen the interpretation.
minor comments (4)
- [Fig. 4 caption] The caption of Fig. 4 labels part (b) as an 'in-plane I-V measurement,' but the text in Section III.D describes J-V measurements through the film thickness (perpendicular to the plane). The label appears to be a misnomer and should be corrected to 'cross-plane J-V' or 'out-of-plane J-V.'
- [III.D] The phrase 'anisotropic metal-insulator-metal structure' is unclear; the structure (ZnS on Pt on heavily doped Si with Cr/Au top contacts) is asymmetric rather than anisotropic. Please clarify the intended meaning.
- [Fig. 2 caption] The caption of Fig. 2(a) lists Al2O3 under 'polycrystalline surfaces,' but the text (Section III.A and Fig. 1) describes Al2O3 deposited by ALD as amorphous. This is inconsistent and should be corrected.
- [III.A, Fig. 1] The abstract states 'out-of-plane texturing across all surfaces,' while the body repeatedly describes the texture as 'weak' (Sections III.A and IV). To avoid overstating the result, use a consistent qualifier such as 'weak out-of-plane texture' in the abstract as well.
Circularity Check
No significant circularity; the paper's derivations are standard parameter extractions and its self-citation of the hPLD method is not load-bearing.
full rationale
The paper's central claims are experimental: hPLD growth of textured ZnS on BEOL-compatible substrates, structural characterization by XRD/XRR/AFM/GIWAXS, and electrical characterization by J-V and MOSCAP measurements. The dielectric constants are extracted from the measured flat capacitance using the standard series-capacitance formula C_total = C_SiO2*C_ZnS/(C_SiO2 + C_ZnS) and the parallel-plate expression, so the reported values (eps_SiO2 = 3.7, eps_ZnS = 5.6) are ordinary parameter extraction from data, not predictions derived from the conclusions. The statement that a flat C-V curve 'points to ZnS being highly intrinsic' is an interpretive inference, not a derivation that reduces to an input; it may be underdetermined by the data (full depletion, blocking contacts, interface states, or series resistance could also produce a flat C-V), but that is a correctness or evidence concern, not circularity. The authors' citation of their own prior work, ref. 18, for the hybrid PLD method is not circular: the method is previously published and independently described, and the current paper applies it to a new material system rather than using the citation to justify the present conclusions. No uniqueness theorem is imported from the authors' prior work, no ansatz is smuggled in via citation, and no known result is renamed as a new organization. Therefore no circular step can be identified under the specified criteria.
Assumptions & free parameters
free parameters (2)
- Dielectric constant of SiO2 (extracted) =
3.7
- Dielectric constant of ZnS (extracted) =
5.6
assumptions (4)
- standard math The series-capacitance formula for a bilayer MOSCAP, C_total = C_SiO2 * C_ZnS / (C_SiO2 + C_ZnS), correctly describes the measured device.
- domain assumption The films are stoichiometric and phase-pure ZnS, maintained by excess sulfur during growth, even though no composition measurement is reported.
- domain assumption A flat C-V curve indicates a highly intrinsic semiconductor with very low electrically active defects.
- domain assumption The 00l XRD reflections arise from wurtzite ZnS and indicate out-of-plane texturing.
Cite this review
Pith. "Pith review of Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates." pith.science (2026). https://pith.science/paper/JO75GRQ5
@misc{pith2026250420028,
author = {Pith},
title = {Pith review of: Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates},
year = {2026},
howpublished = {\url{https://pith.science/paper/JO75GRQ5}},
note = {Machine review of arXiv:2504.20028}
}
abstract
Scaling of transistors has enabled continuous improvements in logic device performance, especially through materials engineering. However, surpassing horizontal limitations in chip manufacturing requires a vertical, third dimension. Three-dimensional integration of high-performance logic demands solving the challenge of low-temperature (less than 450{\deg}C) synthesis of high-mobility n-type and p-type semiconductor thin films for back-end-of-line (BEOL) compatible transistors. Metal oxides, particularly indium oxides alloyed with gallium and tungsten, are promising n-type channel materials, but suitable p-type materials for BEOL remain scarce. Zinc sulfide (ZnS), a wide band-gap semiconductor, shows room-temperature p-type conductivity when doped with copper and crystallizes below 400{\deg}C. Here, we report growth of crystalline ZnS thin films by pulsed laser deposition on amorphous and polycrystalline surfaces including silicon nitride, thermal silicon dioxide, yttrium oxide, hafnium dioxide, sapphire, platinum, and titanium nitride. X-ray diffraction reveals out-of-plane texturing across all surfaces, while grazing incidence wide-angle X-ray scattering probes in-plane crystalline quality. Surface and interface properties are assessed using X-ray reflectivity and atomic force microscopy. Electrical characterization via J-V measurements (ZnS on Pt) and metal-oxide-semiconductor capacitor (ZnS on silicon dioxide) measurements show low leakage current ($10^{-5} A/cm^2$ at 0.40 MV/cm) and bilayer capacitor behavior, suggesting ZnS is highly intrinsic with minimal electrically active defects. Further work on doping ZnS with copper or other p-type elements is needed to realize ZnS as a dopable wide band-gap semiconductor for BEOL integration. This work demonstrates a novel thin-film growth method for sulfide semiconductors under BEOL-compatible conditions.
Figures
Reference graph
Works this paper leans on
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[1]
1 Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates Claire Wu1, Mythili Surendran2, 3, Anika Tabassum Priyoti4, Gokul Anilkumar1, Cheng-Hsien Wu5, Chun-Chen Wang5, Cheng-Chen Kuo5, Harish Kumarasubramanian1, Kenta Lin4, Amari Butler1, Rehan Kapadia4, Xinyu Bao5, Jayakanth Ravichandran1, 3,...
work page 2019
Reviewed August 16, 2026 · model on record in the stance chip above.
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