REVIEW 2 cited by
ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
read the original abstract
We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.
Forward citations
Cited by 2 Pith papers
-
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.
-
DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning
DeepCell fuses AIG and post-mapping netlist views with masked autoencoding, achieving 2.77% lower ECO patch cost and 15-16% lower area-delay product in technology mapping.
Discussion (0). Continue with ORCID to comment.