Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-16T11:45:47.418084Z
Paper Citation Record · LEDGER
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
As of 23 August 2026, this Paper Citation Record lists 5 of 5 outbound references and 0 inbound Pith citation observations for arXiv:2505.03762.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-22T06:32:14.747728+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links
A source-named dated measurement, never combined with another source.
Source: cited_works
Reference resolution
5 of 5 outbound references displayed
- verified exact0
- verified fuzzy5
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
Observation 71f95ae8-f3ab-4cf7-8db1-47b693bfff1c · outbound
This paper cites Cost of application-class processing: Energy and performance analysis of a 1.7-ghz 64-bit risc-v core,.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Cost of application-class processing: Energy and performance analysis of a 1.7-ghz 64-bit risc-v core,
Reference 1
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-08-16T11:45:47.504422Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.
Observation ad4415ae-dfcc-4d1a-a763-8aeb7978ea36 · outbound
This paper cites Using a performance model for su- perscalar cva6 implementation,.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Using a performance model for su- perscalar cva6 implementation,
Reference 2
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-08-16T11:45:47.492012Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.
Observation c8d27653-c64c-431e-8944-b26e85ae221f · outbound
This paper cites Hpdcache: Open-source high- performance l1 data cache for risc-v,.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Hpdcache: Open-source high- performance l1 data cache for risc-v,
Reference 3
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-08-16T11:45:47.478615Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.
Observation bf4cbdd7-aa48-4ca0-81f3-1319f1682707 · outbound
This paper cites Cheshire: A lightweight, linux-capable risc-v host platform,.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Cheshire: A lightweight, linux-capable risc-v host platform,
Reference 4
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-08-16T11:45:47.466115Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.
Observation 30121108-46fe-4629-8a68-4cf6ed3cb20d · outbound
This paper cites Raiderstream: Adapting stream for modern hpc systems,.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Raiderstream: Adapting stream for modern hpc systems,
Reference 5
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-08-16T11:45:47.451603Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.
Pith citing papers
No inbound Pith citation observations are available.