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REVIEW 3 major objections 6 minor 39 references

The High Voltage Splitter board for the JUNO SPMT system

T0 review · 3 major / 6 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read The High Voltage Splitter board for JUNO's small PMTs is claimed to survive the detector's 20-year lifetime.

desk verdict Solid engineering documentation; the reliability section's FIT accounting is wrong and the 20-year claim is unsupported. read the letter →

arxiv 2505.05586 v1 pith:H3OH6LQZ submitted 2025-05-08 physics.ins-det hep-ex

Pablo Walker , Juan Pedro Ochoa-Ricoux , Angel Abusleme , Agustin Campeny , Mathieu Bongrand , Clément Bordereau , José Busto , Anatael Cabrera
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Stéphane Callier Steven Calvez Cédric Cerna Thomas Chabot Po-An Chen Guoming Chen Ziliang Chu Gérard Claverie Christophe De La Taille Charles-Edouard Demonchy Selma Conforti Di Lorenzo Frédéric Druillole Lei Fan Amélie Fournier Yang Han Miao He Patrick Hellmuth Rafael Herrera Yee Hsiung Bei-Zhen Hu Jun Hu Guihong Huang Yongbo Huang Cédric Huss Léonard Imbert Adrienne Jacobi Ignacio Jeria Xiaoshan Jiang Xiaoping Jing Cécile Jollet Jean Jouve Sindhujha Kumaran Loïc Labit Sébastien Leblanc Victor Lebrin Matthieu Lecocq Hongbang Liu Kainan Liu Xiwen Liu Roberto Carlos Mandujano Anselmo Meregaglia Diana Navas-Nicolas Zhe Ning Yujie Niu Frédéric Perrot Rebin Karaparambil Rajan Reem Rasheed Abdel Rebii Mathieu Roche Cayetano Santos Mariangela Settimo Yunhua Sun Jingzhe Tang Giancarlo Troni Benoit Viaud Chung-Hsiang Wang Jian Wang Yangfu Wang Zhimin Wang Diru Wu Jacques Wurtz Wan Xie Jilei Xu Jinghuan Xu Meihang Xu Chengfeng Yang Frédéric Yermia Junwei Zhang Siyuan Zhang
This is my paper · ORCID
classification physics.ins-dethep-ex
keywords JUNOSPMTHighVoltageSplitterPMTreadoutelectronicsacceleratedagingArrheniusmodelfailurerateFITprintedcircuitboarddesign
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper documents the design, qualification, and mass production of the High Voltage Splitter (HVS), the first board in the readout chain of JUNO's small photomultiplier (SPMT) system. Its central claim is that the HVS is fit for deployment: it respects the analog noise and distortion budget (below one tenth of a single photoelectron, roughly 200 microvolts), keeps crosstalk and reflections in the per-cent range, passes all 430 production functional tests, and is expected to operate reliably for JUNO's 20-year lifetime. A sympathetic reader would care because 25,600 PMTs in an inaccessible underwater detector cannot be serviced; the board's longevity is a condition for the experiment's physics program, from neutrino mass ordering to supernova neutrinos.

What carries the argument

The central object that carries the argument is the HVS board itself (version 3.2), an eight-layer, 365 mm by 190 mm FR-4 PCB with 64 channels, 50 ohm impedance-controlled traces, 4.77 mm high-to-low voltage clearances, and Pentelast-712 compound encasing the decoupling capacitors and MCX connectors. Three design mechanisms do the work: the 20 MOhm series resistors, which limit the current draw of a shorted channel to 75 microamps so a subgroup tolerates two failures; the reverse-biased BAV99S protection diodes, which clamp ESD transients before they reach the CATIROC front-end chip; and the C0G 3.9 nF decoupling capacitor, selected for its voltage-stable capacitance and minimal overshoot. The paper's quantitative claim of 20-year reliability, however, is carried not by the board design alone but by the Arrhenius acceleration factor that converts oven hours into equivalent device hours at ambient temperature.

What would settle it

Age replicated HVS boards at three different temperatures below the compound's melting point, for example 60, 70, and 80 degrees Celsius, long enough to observe actual failures, and fit the Arrhenius plot to obtain the true activation energy. If that energy is below about 1 eV, the quoted FIT values and the 20-year expectation are over-optimistic; if it is above, they are conservative. A complementary single run at a higher temperature with the Pentelast-712 compound present would reveal whether compound melting or outgassing introduces failure modes absent from the current test.

Watch

Extended reading notes

Core claim

The paper's claim is that a carefully constrained board can simultaneously deliver high voltage (up to 1.42 kV) to 64 SPMTs, decouple the roughly 2 mV single-photoelectron pulses, keep all signal artifacts below the 1/10-SPE threshold, and survive continuous underwater operation for the experiment's 20-year design life. The evidence is a chain of measured numbers: worst-case crosstalk of 1.6% positive and 1.1% negative, reflection artifacts at 0.9% and 0.3%, FIT values of 10.4 for the high-voltage diodes, 10.4 and 0.4 for the capacitors, 53 for the HVUs, and 900.1 for the board itself, against a system requirement of 1900; and a production yield of 430/435 boards passing functional and burn-in testing. The reliability figure rests on an accelerated-aging extrapolation using the Arrhenius equation with an activation energy of 1 eV, chosen, in the authors' words, in absence of empirical data.

Load-bearing premise

The 20-year reliability expectation assumes that the Arrhenius law with an activation energy of 1 eV, chosen in absence of empirical data, correctly translates a 689.5-hour test at 100 degrees Celsius into 291 years of operation at 21 degrees Celsius, and that the failure modes of a board aged without its insulating compound and with its HVUs outside the oven match those of the installed board.

Editorial extensions

If this is right

  • The board meets the SPMT system's analog budget: noise and distortion below 200 microvolts, so false triggers from reflections or crosstalk are suppressed at the single-photoelectron threshold.
  • The redundancy scheme means that up to two shorted PMTs per 16-channel subgroup can be tolerated before the HVU saturates, so single-channel failures degrade the detector gracefully.
  • With measured FIT values below 1900, the probability of losing more than 10% of the readout channels in the first six years is expected to stay within the system requirement.
  • The 430/435 production yield and the burn-in plus automated functional testing provide the quality assurance needed to install the boards in an inaccessible underwater detector.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the assumed 1 eV activation energy is an overestimate, then the same hours at 100 degrees Celsius correspond to far fewer equivalent years at 21 degrees Celsius; a measurement of the true activation energy from multi-temperature aging would settle the 20-year expectation directly.
  • The observed increase in reflection amplitude after aging hints that dielectric aging affects impedance matching; monitoring the in-situ SPE waveform over the first years of JUNO operation would test whether the same drift appears at ambient temperature.
  • The same board design and reliability methodology could transfer to other long-lived underwater or inaccessible detectors, but only if the aging extrapolation is anchored to measured activation energies for each material class (diode, capacitor, PCB laminate, encapsulation compound).
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This paper documents the design, performance, and production qualification of the High Voltage Splitter (HVS) board for the JUNO SPMT system. The HVS provides high-voltage biasing to 3-inch PMTs and decouples the physics signal for readout. The authors describe the system-level constraints, circuit and physical layout, signal-integrity measurements (SPE waveforms, reflections, crosstalk), ESD protection validation, accelerated-aging reliability estimates, and the production/QC campaign in which 430 of 435 boards passed functional testing. The paper's stated central claim is that the HVS is expected to operate reliably throughout JUNO's 20-year operational lifetime, based on measured compliance with system requirements and on component FIT values that are reported to be below the derived 1900 FIT budget.

Significance. A documented, mass-produced detector front-end board is valuable to the instrumentation community, and the paper has real strengths: the design rationale is detailed, the signal-integrity measurements are presented with enough setup information to be reproducible, the production testing procedure is clearly described, and the limitations of the accelerated-aging test are at least partially acknowledged. If the reliability accounting were correct, the paper would be a useful reference for high-voltage electronics in large neutrino detectors. However, the central reliability conclusion is currently not supported by the FIT analysis as presented: per-component FIT values are compared against a system-level per-UWB budget without summing over the components in a UWB, and the extrapolation to 20 years depends on an assumed activation energy. These issues are load-bearing for the paper's main claim and require substantive revision.

major comments (3)
  1. [Section 6.2 and Section 8] The 1900 FIT requirement is derived in Eq. (7) from a per-UWB failure budget of 10% loss after six years, but the paper compares each component type's FIT individually to 1900 instead of summing the FITs of all components in one UWB. A UWB contains two HVS boards, each servicing 64 channels. Weighting the reported per-component FITs by the component counts on one UWB gives 2×900.1 (PCB) + 16×53 (HVU) + 16×10.4 (R5000F diodes) + 128×10.4 (decoupling capacitors) ≈ 4146 FIT, which already exceeds 1900 before including ESD diodes, series resistors, connectors, the ABC board, or the GCU. Even using the vendor-provided FIT values for the diodes and capacitors (0.1 and 0.4, respectively), the sum is approximately 2700 FIT. The conclusion in Section 8 that 'the HVS is expected to operate reliably throughout JUNO's 20-year operational lifetime' therefore does not follow from the data as presented; the budget must be applied to the summed system FIT.
  2. [Table 3 and Section 6.4] The reported capacitor FIT of 10.4 is inconsistent with the stated test conditions and with Eqs. (1)-(6). Using Ta=295.15 K, Te=373.15 K, Ea=1 eV, D=100 capacitors, H=122.8 h, and r=0 observed failures, the 90%-confidence FIT is χ²(0.9,2)/(2·EDH)·10^9 ≈ 50.6, not 10.4. The value 10.4 corresponds to the diode test duration H=598.5 h. This arithmetic discrepancy should be corrected; with the corrected capacitor FIT, the summed system FIT from the previous comment becomes even larger.
  3. [Sections 6.3, 6.4, and 6.6] The 20-year reliability projection is not robust to the assumed activation energy. For the diodes, capacitors, and PCB, Ea=1 eV is adopted 'in absence of empirical data' (Sections 6.3, 6.4, and 6.6), while Section 6.1.1 quotes 0.7 eV as the generic value for diode-type semiconductors. If Ea=0.7 eV, the single-board PCB test (D=1, H=689.5 h, Te=373.15 K) gives Af≈315 and a 90%-confidence FIT of about 1.1×10^4, already far above 1900; the capacitor FIT similarly rises to about 600. In addition, the PCB aging test omits the Pentelast-712 compound and keeps the HVUs outside the oven, so it does not exercise the insulation system exactly as installed. The paper should either provide measured Ea values, a sensitivity scan over plausible Ea values, or a clearly stated conservatism argument before claiming a 20-year lifetime.
minor comments (6)
  1. [Section 5.1] The phrase 'usedtousedtocommunicateandcontrol' contains a duplicated word; it should read 'used to communicate and control'.
  2. [Section 5.4] The worst-case crosstalk peaks (1.6% positive and 1.1% negative) are quoted without uncertainties or the number of channel pairs and measurement repetitions used; please provide at least the sample size and a statement of measurement repeatability.
  3. [Section 5.3] The reflection artifacts are quoted as 'roughly 0.9% and 0.3%' without specifying the cable length, trigger settings, and number of channels over which the maximum was observed; the text should state these conditions explicitly.
  4. [Section 6.6] The equivalence of 689.5 h at 100 °C to 291 years is stated without showing the calculation; please state the assumed ambient temperature, activation energy, and acceleration factor at the point of the claim.
  5. [Section 2.1.6 and Section 5.2] The requirement is quoted as 'below 1/10 of an SPE' and separately as 'roughly 200 μV', while Section 5.2 gives a typical SPE amplitude of about 2 mV; please clarify whether the 1/10 criterion is applied to peak amplitude, RMS noise, or both.
  6. [References] Refs. [18] and [24] are listed as 'Paper in preparation', and key reliability inputs in Sections 6.3-6.5 rely on private correspondence [35,36]; these limitations should be noted where the values are used, as they currently reduce the reproducibility of the reliability assessment.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the HVS performance and reliability claims are tested against external system-level benchmarks, not defined by the claimed conclusion.

full rationale

The paper's central claims, namely signal integrity within 1/10 of a single photoelectron and reliable operation over JUNO's 20-year lifetime, are supported by measurements against externally set requirements. Section 2.1.6 fixes the 1/10-SPE distortion and noise budget from the CATIROC trigger threshold at 1/3 of an SPE, and Section 6.2 derives FIT < 1900 from JUNO's system-level requirement of at most 10% UWB loss after six years; these are outside inputs, not outputs of the HVS design. Crosstalk (Section 5.4), reflections (Section 5.3), and SPE waveforms (Section 5.2) are direct measurements, and component FIT values are computed from accelerated-aging device-hours using Eq. (2), rather than being fitted to the final reliability conclusion. The activation energy of 1 eV is an assumed extrapolation parameter, explicitly stated as chosen 'in absence of empirical data,' so any concern about the 20-year extrapolation is a premise uncertainty rather than circularity. The citations to in-preparation collaboration papers (Refs. [18] and [24]) concern companion readout and PMT instrumentation, and they are not load-bearing for the HVS-specific measurements presented here. No equation is defined in terms of the claim being derived, so no circular step can be exhibited.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The paper's central claims rest mostly on direct measurements, so the ledger is light. The only load-bearing numerical inputs are the assumed activation energies and the HTOL acceleration model that convert short hot tests into 20-year FIT values. The high-voltage insulation design relies on standard FR-4 dielectric strength and IPC-2221B clearance guidance. No new physical entities are introduced.

free parameters (2)
  • Activation energy Ea for diode, capacitor, and PCB FIT estimates = 1 eV (assumed, not measured)
    Used in Eq. (1) to convert 100 degrees Celsius HTOL results into 20-year FIT values for diodes, capacitors, and the PCB (Sections 6.3, 6.4, 6.6). The Arrhenius factor is exponential, so the reported FIT numbers (10.4, 10.4, 0.4, 900.1) scale sensitively with this choice.
  • Activation energy Ea for HVUs = 0.63 eV (measured in prior LPMT development, not shown here)
    Basis of the HVU FIT of 53 (Section 6.5). The measurement is referenced from out-of-scope prior work, so the value is an input to this paper rather than a result demonstrated here.
assumptions (4)
  • domain assumption The Arrhenius HTOL model correctly describes HVS failure modes at accelerated temperature
    Section 6.1.1, Eq. (1). The entire 20-year reliability claim rests on this acceleration model being valid for these components and failure modes.
  • standard math Chi-squared counting statistics apply to zero-failure samples
    Eqs. (4) and (5), Section 6.1.2. Standard treatment, but it produces only statistical upper bounds, not true failure rates.
  • domain assumption FR-4 dielectric strength of 360 V/mil and IPC-2221B clearance tables are an appropriate design basis
    Sections 4.2 and 4.3. The board's high-voltage insulation adequacy rests on these standards and on the assumption that FR-4 properties hold over 20 years.
  • domain assumption Overshoot measurements at 900 V bias with a 10 m cable are representative across the full 900-1300 V operating range
    Section 3.5.2: the decoupling capacitor selection was based on experimental results at a single bias point and cable length, without a systematic scan.

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Cite this review

Pith. "Pith review of The High Voltage Splitter board for the JUNO SPMT system." pith.science (2026). https://pith.science/paper/H3OH6LQZ

@misc{pith2026250505586,
  author       = {Pith},
  title        = {Pith review of: The High Voltage Splitter board for the JUNO SPMT system},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/H3OH6LQZ}},
  note         = {Machine review of arXiv:2505.05586}
}
read the original abstract

The Jiangmen Underground Neutrino Observatory (JUNO) in southern China is designed to study neutrinos from nuclear reactors and natural sources to address fundamental questions in neutrino physics. Achieving its goals requires continuous operation over a 20-year period. The small photomultiplier tube (small PMT or SPMT) system is a subsystem within the experiment composed of 25600 3-inch PMTs and their associated readout electronics. The High Voltage Splitter (HVS) is the first board on the readout chain of the SPMT system and services the PMTs by providing high voltage for biasing and by decoupling the generated physics signal from the high-voltage bias for readout, which is then fed to the front-end board. The necessity to handle high voltage, manage a large channel count, and operate stably for 20 years imposes significant constraints on the physical design of the HVS. This paper serves as a comprehensive documentation of the HVS board: its role in the SPMT readout system, the challenges in its design, performance and reliability metrics, and the methods employed for production and quality control.

Figures

Figures reproduced from arXiv: 2505.05586 by the authors.

Figure 1
Figure 1. Schematic view of the JUNO detector [5]. 1. Introduction 1.1. The JUNO experiment The Jiangmen Underground Neutrino Observatory, or simply JUNO, is a multi-purpose neutrino experiment lo￾cated in southern China, installed within a cavern with a 650 m overburden (1800 m.w.e.). The main objective of the experiment is to determine the neutrino mass ordering with a 3𝜎 significance within roughly six years of data taking… view at source ↗
Figure 3
Figure 3. Block diagram of the SPMT readout system. the last iteration of the HVS PCB (version 3.2), which was installed in JUNO. An overview of the SPMT system can be found in Ref. [5], while a more comprehensive review of the readout electronics is presented in Ref. [18]. The document is broadly divided into three parts. The rest of Section 1 provides an overview of the functionality of the SPMT readout system and the vario… view at source ↗
Figure 4
Figure 4. Exploded view of the main components of the UWB and associated electronics [5] [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (27 more)
Figure 5
Figure 5. Figure 5: The readout electronics connected to the inside of the UWB lid during integration. the outside of the UWB, they are connected to the SPMTs via long coaxial cables (5 m or 10 m), and on the inside, to the two HVS boards via short 15 cm coaxial cables. The un￾derwater co…
Figure 7
Figure 7. Figure 7: Underside and pinout of the HVU. The combined output from the HVUs is then connected to 16 individual SPMT channels via series resistors. Fol￾lowing each series resistor, the HVS connects to the SPMT through a long coaxial cable, which can be either 5 m or 10 m in leng…
Figure 8
Figure 8. Figure 8: Worst case scenario for channel failure. The output of the HVS is shorted to the ground, while the corresponding HVU is outputting its maximum operational voltage. bias. The selected component has a peak reverse voltage of 5 kV, and a roughly 2 V forward voltage drop a…
Figure 9
Figure 9. Figure 9: Illustration of the capacitance variation versus applied DC voltage of a generic 1 kV X7R (Class II) MLCC capacitor. The curve was derived from trends across various manufacturers. require a larger form factor for the same capacitance value compared to Class II capacit…
Figure 10
Figure 10. Figure 10: Average SPE signals, normalized to unit amplitude, for different capacitor candidates. The effective capacitance of X7R capacitors can be expected to be lower than their nominal value. Signal has been digitally filtered to remove some unwanted aggressor frequencies pr…
Figure 11
Figure 11. Figure 11: Single-channel schematic with and without protec￾tion diodes. suddenly drops to zero, the instantaneous voltage of the ca￾pacitor is retained, causing a sudden drop in voltage in node 𝑉𝐵 equal in magnitude to the voltage stored in the capacitor and of negative amplitu…
Figure 13
Figure 13. Figure 13: Emulation PCB used to test the protection diodes. Although the protection diodes significantly reduce the voltage measured on the output of the HVS, the measured voltage remains high enough to raise concerns about poten￾tial damage to the CATIROC chips, requiring furt…
Figure 12
Figure 12. Figure 12: Induced shorts and ESD measurements. The diode connected to the positive power rail is biased at 2.8 V, as shown in [PITH_FULL_IMAGE:figures/full_fig_p009_12.png]
Figure 14
Figure 14. Figure 14: Layout of the HV-Splitter version 3.2. The color coding at the bottom references the signal layers [PITH_FULL_IMAGE:figures/full_fig_p010_14.png]
Figure 15
Figure 15. Figure 15: Layer stackup (a) Ground cutouts underneath SMD decoupling capacitors (b) Internal plane clearance for THD diode pads [PITH_FULL_IMAGE:figures/full_fig_p011_15.png]
Figure 16
Figure 16. Figure 16: Cutouts and clearances on the ground planes for high-voltage components. The green areas represent the absence of copper on the internal layers. Similarly, clearances are also used for high-voltage vias. The two outer layers are used for low-voltage signal routing and…
Figure 18
Figure 18. Figure 18: QTE connector and mating cable, used for the interfaces between the HVS and the ABC (shown in the image) and the GCU. tear-off that is common with surface-mount soldering. The hybrid mounting style provides a robust connection while keeping the inner layers around the…
Figure 19
Figure 19. Figure 19: Controlled-depth milling slots. (a) Capacitors and milling slot (b) MCX connectors [PITH_FULL_IMAGE:figures/full_fig_p014_19.png]
Figure 22
Figure 22. Figure 22: Individual SPE events measured using a 10m coaxial cable. The noise present in these measurements does not represent the noise of the JUNO SPMT system, as it is influenced by power supply noise (i.e., the 24 V power supply used to power HVUs) and electromagnetic inter…
Figure 23
Figure 23. Figure 23: Average SPE waveform for a 10m coaxial cable. Every curve was computed by averaging 1000 individual SPE signals and removing the systematic offset. 5.2. Single photoelectrons The lowest energy and most common events that are detected by the SPMTs are SPEs. At nominal …
Figure 24
Figure 24. Figure 24: Average SPE waveform for a 5m coaxial cable on a board without impedance matching. The SPMT used is biased at slightly higher than nominal gain [PITH_FULL_IMAGE:figures/full_fig_p016_24.png]
Figure 26
Figure 26. Figure 26: show a close-up of the normalized waveform for two pairs of channels. The layout of the analog traces on the HVS is symmetrical, and these pairs of channels were selected due to them having an identical layout, although mirrored. From the plots, it appears that there …
Figure 27
Figure 27. Figure 27: Crosstalk on a victim-aggressor pair [PITH_FULL_IMAGE:figures/full_fig_p017_27.png]
Figure 28
Figure 28. Figure 28: Crosstalk between an aggressor channel, namely channel 𝑛, and adjacent channels with increased channel separation. the available space, the high-voltage clearance and the fixed trace width due to impedance matching. To qualify the crosstalk behavior of the HVS, two ch…
Figure 31
Figure 31. Figure 31: Schematic of the diode board, where 100 resistors and diodes are connected in parallel [PITH_FULL_IMAGE:figures/full_fig_p019_31.png]
Figure 33
Figure 33. Figure 33: Capacitance changes after aging [PITH_FULL_IMAGE:figures/full_fig_p020_33.png]
Figure 32
Figure 32. Figure 32: PCB containing 100 high-voltage capacitors con￾nected in parallel. Jumpers are placed on both ends of each capacitor in order to disconnect them from the circuit if necessary. a measurement in the tens of µA, but it slowly decreased, reaching submicron levels at aroun…
Figure 34
Figure 34. Figure 34: Single PCB used for the accelerated aging test of the HV-Splitter at 100◦C. The use of the Pentelast-712 compound was omitted and the HVUs placed outside the oven, as temperatures above 70◦C can melt the compound. therefore increase the time acceleration factor, a cus…
Figure 35
Figure 35. Figure 35: Average normalized signal measurements for a 10m coaxial cable for all 64 channels of the HVS superimposed, performed after the accelerated aging test. components on the board. Considering a confidence level of 90%, the FIT value can be computed to be 900.1. P Walker …
Figure 36
Figure 36. Figure 36: shows one HVS connected to the burn-in setup. A single 50 Ω termination is used per group of 16 channels to load each HVU, as opposed to loading each individual channel, to simplify the connection and testing process. The communication and power delivery are handled b…
Figure 37
Figure 37. Figure 37: The HVS Test Board connected to and mounted on top of a HVS board. testing after they had undergone burn-in. For this purpose, a custom PCB was designed, referred to as the HVS Test Board (HVSTB), along with the development of custom firmware and software to run a ful…
Figure 38
Figure 38. Figure 38: Simplified schematic of the HVS and the testing subcircuits of the HVSTB. The multiplexers shown in the schematic are in fact multiplexer banks, and the combined operation of each bank is that of a single analog multiplexer with a 64:1 ratio. signal path; and (iii) th…

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Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.