Pith. sign in

REVIEW 1 cited by

Understanding Stragglers in Large Model Training Using What-if Analysis

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2505.05713 v2 pith:UHFQFZGH submitted 2025-05-09 cs.DC cs.LG

classification cs.DCcs.LG
keywords stragglerstraininganalysisbytedancelargemodeloftenwhat
verification ladder T0 review T1 audit T2 compute T3 formal
0 comments
read the original abstract

Large language model (LLM) training is one of the most demanding distributed computations today, often requiring thousands of GPUs with frequent synchronization across machines. Such a workload pattern makes it susceptible to stragglers, where the training can be stalled by few slow workers. At ByteDance we find stragglers are not trivially always caused by hardware failures, but can arise from multiple complex factors. This work aims to present a comprehensive study on the straggler issues in LLM training, using a five-month trace collected from our ByteDance LLM training cluster. The core methodology is what-if analysis that simulates the scenario without any stragglers and contrasts with the actual case. We use this method to study the following questions: (1) how often do stragglers affect training jobs, and what effect do they have on job performance; (2) do stragglers exhibit temporal or spatial patterns; and (3) what are the potential root causes for stragglers?

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. SLOTH: Lightweight Detection and Localization of On-Chip Fail-Slow Failures for DNN Accelerators

    cs.AR 2025-10 conditional novelty 6.0 of 10

    A simulation-based framework using compiler-inserted probes, a two-stage sketch, and a PageRank-style ranking detects on-chip fail-slow cores/links at ~86.8% accuracy with ~116x trace compression.

Pith tools