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REVIEW 2 major objections 5 minor 47 references

Time-tagging data acquisition system for testing superconducting electronics based on an RFSoC and custom analog frontend

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A custom RFSoC-based data acquisition system with a thermal-noise-limited analog frontend and time-tagging firmware drove a superconducting nanowire shift register at 200 MHz, nearly three times the 83 MHz reached with commercial…

desk verdict A useful, honestly-engineered open-source DAQ for nanocryotron testing, but the 200 MHz shift-register speed claim rests on visual waveform inspection rather than a quantitative error-rate measurement. read the letter →

arxiv 2505.21714 v4 pith:RQ5MSEX5 submitted 2025-05-27 physics.ins-det cond-mat.supr-con

Reed A. Foster , Stephen Kandeh , Owen Medeiros , Alejandro Simon , Matteo Castellani , Karl K. Berggren This is my paper · ORCID
classification physics.ins-detcond-mat.supr-con PACS 07.05.Hd
keywords Digitalelectroniccircuitssignalprocessing(DSP)DataacquisitionconceptsreductionmethodsRFSoCsuperconductingnanocryotronstime-tagging
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that for many novel superconducting circuits the test equipment, not the circuit, is the speed bottleneck, and that a single integrated instrument can remove it. The authors build a data acquisition system around an RFSoC with multi-gigasample-per-second converters: a custom analog frontend gives a thermal-noise-limited receive path with roughly 50 dB of dynamic range, and custom FPGA firmware saves only short, timestamped waveform snippets around threshold-crossing events. Used on a previously characterized superconducting-nanocryotron binary shift register, the system clocked the circuit at 200 MHz, compared with an 83 MHz ceiling the authors attribute to the commercial arbitrary-waveform-generator/digitizer setup, at about one-seventh the cost. If the claim holds, the contribution is a reusable, open-source way to probe the intrinsic speed limits and failure modes of nanocryotron circuits and similar stateful electronics.

What carries the argument

The load-bearing element is the real-time sample discriminator implemented in FPGA firmware. It compares the digitized stream against a high (start) threshold and a low (stop) threshold with hysteresis; any sample above the high threshold begins capture and capture only ends when all samples in a processing batch fall below the low threshold. The discriminator saves a runtime-configurable number of samples before and after each event via delayed data paths and timestamps each capture with a monotonic time counter plus a sample index, so the original waveform can be reconstructed without storing every sample. Start and stop events from one channel can be routed to another through a crossbar, enabling trigger sharing, for example using a filtered version of a signal to capture the raw version. The custom analog frontend, built around a low-noise amplifier with a 3 dB noise figure, supplies the measured signal-to-noise-and-distortion floor of roughly 50 dB and lets the system operate without external amplification.

What would settle it

Run the same two-loop shift register at 200 MHz with the RFSoC system while counting bit errors from the timetag data over many clock cycles, and repeat the 83 MHz measurement with the identical amplifier chain but swapping only the stimulus source and digitizer. If the error rate at 200 MHz is not low, or if the commercial equipment also reaches 200 MHz with the upgraded frontend, the paper's attribution of the speed limit to test equipment would be overturned.

Watch

Extended reading notes

Core claim

The authors set out to show that integrated signal generation and real-time waveform processing can test circuits whose subcomponents have no standardized interfaces, and can do so faster than separate commercial instruments. Their system combines the RFSoC's 6 GS/s digital-to-analog converters and 4 GS/s analog-to-digital converters with custom firmware: a real-time sample discriminator performs hysteretic threshold comparison on batches of eight samples, records a timestamp and the raw voltage samples around each event, and discards the rest, so only data of interest leaves the FPGA. With this system they observed sub-200 ps output rise times and operated a two-loop superconducting nanowire binary shift register at 200 MHz, which they state was the highest frequency at which they observed it operate; the same circuit had previously topped out at 83 MHz with commercial (COTS) equipment. They conclude that the earlier ceiling was largely a sample-rate limitation of the test equipment rather than a property of the circuit, and that the data acquisition system can push circuits beyond their previously measured operating speeds.

Load-bearing premise

The central claim rests on treating the 83 MHz ceiling as a test-equipment limit and the 200 MHz operation as genuine switching, even though the switching at 200 MHz was judged from digitized waveforms and the comparison used a different amplifier chain in the commercial setup.

Editorial extensions

If this is right

  • The same shift-register circuit operated at 200 MHz with the RFSoC system, showing the prior 83 MHz limit was largely imposed by the commercial test equipment's sample rate.
  • The time-tagging discriminator stores only events of interest, so locating errors and debugging can be done without moving tens to hundreds of gigabytes of waveforms.
  • At 4 GS/s the system resolves sub-200 ps rise times and reveals artifacts such as clock-edge differentiation caused by excess inductance, which are invisible to 500 MS/s capture.
  • The firmware, software, and analog frontend schematics are released under an open-source license, and the hardware costs about $16,000, roughly one-seventh the cost of the compared commercial configuration.
  • The same architecture can test multiple inputs and outputs simultaneously, which matters for stateful logic circuits whose behavior depends on combined stimuli.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The 200 MHz figure is based on visual interpretation of voltage traces; a quantitative bit-error-rate measurement at that clock rate would be needed to confirm the circuit truly operates there rather than producing switching-like artifacts.
  • The 83 MHz baseline came from a setup using a different amplifier chain (external LC amplifiers), so part of the speed gain could come from the improved analog frontend rather than the RFSoC sample rate alone; the paper asserts, rather than isolates, that the COTS AWG was the sole limit.
  • The time-tagging and trigger-sharing design should transfer directly to other event-sparse, high-rate measurements such as superconducting nanowire single-photon detectors, where it could enable pulse-shape-based particle identification and time-walk correction.
  • If the claimed speed-up is real, it follows that reported operating frequencies of many novel-device circuits may understate their intrinsic limits, and researchers should treat test-equipment ceilings as a design variable rather than a fixed constraint.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper describes a custom, open-source time-domain data acquisition system built around an RFSoC (ZCU111) with a custom analog frontend. The FPGA firmware implements real-time sample discrimination and timetagging for sparse data capture, and the system includes multi-GS/s AWG signal generation. The analog frontend is characterized in loopback, showing improved SINAD and a noise floor consistent with the specified LNA noise figure. As a demonstration, the authors use the system to test a previously characterized superconducting nanocryotron shift register and report operation at 200 MHz, compared with 83 MHz with commercial COTS equipment, claiming a nearly three-fold increase in maximum clock speed.

Significance. If the central speed claim is quantitatively established, this is a valuable contribution: a cost-effective, reproducible DAQ platform (with released firmware, software, and schematics) that combines wideband stimulus and time-tagging acquisition, potentially enabling error-rate studies of novel superconducting circuits at speeds beyond typical sub-GS/s COTS equipment. The thermal-noise-limited analog frontend and the real-time sample-discriminator firmware are useful building blocks for detector readout and nanocryotron logic testing. The open-source release is a concrete strength. However, the headline demonstration—operation of the shift register at 200 MHz—currently rests on visual waveform inspection and is not supported by an error-rate or pattern-verification measurement, so the significance of the speed claim is not yet fully established.

major comments (2)
  1. [Section 4, Fig. 5c(iii)] The claim that the shift register 'could operate at 200 MHz' is supported only by visual interpretation of captured waveforms, with no quantitative correctness criterion. The text itself states that at 200 MHz the fast clock edge 'results in substantial voltage pulses even when the nanocryotron does not switch,' making it 'more difficult to determine when the nanocryotron actually switched.' Since apparent output pulses can arise from clock feedthrough and differentiation effects without a true state transition, the displayed traces are insufficient to demonstrate that the circuit produced the correct output sequence. Given that the system is explicitly designed for event counting and time-tagging, a quantitative check—e.g., a known input pattern with a pre-specified acceptance threshold, or a bit-error-rate measurement at 200 MHz—is necessary to support the headline speed claim.
  2. [Section 4, Fig. 5c] The comparison between the custom system (200 MHz) and the COTS system (83 MHz) is confounded by differences in the amplifier chain: the COTS measurement used two external RF-Bay LNA-2500 amplifiers per output (six total), while the custom measurement used the on-board low-noise amplifier in the custom analog frontend. The paper asserts that the COTS AWG sample rate was the limiting factor, but it does not demonstrate that the different amplification paths could not also contribute to the observed maximum operating frequency. To make the speed comparison a clean demonstration of the DAQ's capability, the authors should either use the same amplifier chain in both configurations or explicitly characterize the effect of amplifier bandwidth/gain on the measured operating margin, for example by measuring the shift register error rate at matched signal levels with both systems.
minor comments (5)
  1. [Abstract and Section 4] The abstract quotes the COTS maximum clock rate as 80 MHz, while Section 4 and Fig. 5c state 83 MHz; please make these numbers consistent.
  2. [Abstract and Section 4] The phrase 'nearly three-times' (abstract) and 'nearly three-fold' (Section 4) is inaccurate for 200/83 ≈ 2.4; suggest using 'about 2.4-times' or similar.
  3. [Section 5] The opening sentence contains a typo: 'data acqusition' should be 'data acquisition', and 'dataacqusitionsystem' is missing a space.
  4. [Figure 4b] The caption states that the spectra are shifted by 1 MHz in the inset for clarity, but it is not clear what is being clarified; please specify the purpose of the shift (e.g., to avoid overplotting the two traces).
  5. [Section 2.4.1] The description of the POSTCAPTURE state could be clarified with a timing diagram showing the relationship between the digital trigger, startd, and stopd signals, since the current text is somewhat abstract.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the DAQ benchmarks are direct measurements against external references, and no prediction is derived from fitted inputs.

full rationale

The paper's claims are experimental demonstrations rather than derivations from fitted parameters. The analog frontend is characterized against a passive breakout board and the thermal noise floor; Section 3 states that the measured noise floor of approximately -79 dBm is consistent with the specified 3 dB noise figure of the TRF37D73 amplifier, an independent datasheet value. The central speed comparison (200 MHz vs. 83 MHz) is a direct measurement: the 83 MHz baseline comes from a prior characterization with commercial Keysight equipment in Ref. [13], and the 200 MHz point is a new observation with the custom RFSoC system, so neither number is defined in terms of the other. The sample-discriminator demonstration is an implementation validation, not a prediction. The only same-group self-citation that is load-bearing is Ref. [13] for the COTS baseline, but that baseline is an empirical result obtained with independent commercial instrumentation and is not equivalent to the present system's outputs. A separate verification concern, noted in Section 4, is that at 200 MHz clock feedthrough produces voltage pulses even when the nanocryotron does not switch, making the 'operate at 200 MHz' claim dependent on visual waveform interpretation rather than a quantitative error-rate measurement; this is a correctness and rigor issue, not circularity.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

No fitted constants enter the central claim, and no new physical entities are postulated. The system is an engineering integration of known components. The load-bearing assumptions are domain-level: vendor converter specs, the validity of the shift-register test vehicle, the attribution of the COTS limit to the AWG, and standard thermal noise physics.

free parameters (1)
  • Sample discriminator high/low thresholds and pre/post-event delays (tau_pre, tau_post) = set to zero for the 200 MHz test; threshold levels shown in Fig. 5c
    Runtime-configurable test settings chosen by the user for the demonstration. They affect which snippets are saved, not a derived physical quantity, and do not enter the central claim as fitted constants.
assumptions (4)
  • domain assumption The XCZU28DR RFSoC data converters meet their specified 12-bit 4 GS/s ADC and 14-bit 6 GS/s DAC performance in the assembled system.
    Invoked throughout Section 2; converter linearity and bandwidth are taken from the vendor rather than independently verified by the authors.
  • domain assumption The two-loop superconducting shift register from ref [13] is a valid test vehicle, and the digitized voltage patterns at 200 MHz correspond to correct shift-register operation.
    Section 4 interprets the waveforms as correct behavior despite the acknowledged clock-differentiation artifact that obscures switching moments.
  • domain assumption The 83 MHz ceiling of the COTS setup was caused entirely by AWG sample-rate limitations, so the 200 MHz result can be attributed to the new DAQ system rather than to differences in the amplification chain.
    Asserted in Section 4 ('due to sample rate limitations of the AWG'); no control experiment sweeps the COTS AWG above 83 MHz.
  • standard math Standard thermal noise model: -81 dBm noise floor for 2 GHz bandwidth at 50 ohm, consistent with a 3 dB amplifier noise figure.
    Used in Section 3 to interpret the measured -79 dBm noise floor as thermal-noise-limited.

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Cite this review

Pith. "Pith review of Time-tagging data acquisition system for testing superconducting electronics based on an RFSoC and custom analog frontend." pith.science (2026). https://pith.science/paper/RQ5MSEX5

@misc{pith2026250521714,
  author       = {Pith},
  title        = {Pith review of: Time-tagging data acquisition system for testing superconducting electronics based on an RFSoC and custom analog frontend},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RQ5MSEX5}},
  note         = {Machine review of arXiv:2505.21714}
}
read the original abstract

Novel electronic devices can often be operated in a plethora of ways, which makes testing circuits comprised of them difficult. Often, no single tool can simultaneously analyze the operating margins, maximum speed, and failure modes of a circuit, particularly when the intended behavior of subcomponents of the circuit is not standardized. This work demonstrates a cost-effective time-domain data acquisition system for electronic circuits that enables more intricate verification techniques than are practical with conventional experimental setups. We use high-speed digital-to-analog converters and real-time multi-gigasample-per-second waveform processing to push experimental circuits beyond their maximum operating speed. Our custom time-tagging data capture firmware reduces memory requirements and can be used to determine when errors occur. The firmware is combined with a thermal-noise-limited analog frontend with 50 dB of dynamic range. Compared to currently available commercial test equipment that is seven times more expensive, this data acquisition system was able to operate a superconducting shift register at a nearly three-times-higher clock frequency (200 MHz vs. 80 MHz).

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Reference graph

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