A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs

Alexis Maras; Barry de Bruin; Dimitrios Soudris; Georgios Alexandris; Henk Corporaal; Manil Dev Gomony; Panagiotis Chaidos; Sotirios Xydis

REVIEW 3 major objections 5 minor 28 references

A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read Adding DRUM approximate multipliers and 0.6 V voltage islands to an R-Blocks CGRA cuts energy by about 30% with a 2% area overhead, while keeping MobileNetV2 output error small.

desk verdict A plausible end-to-end framework for approximate CGRAs with a novel per-channel mapping idea, but the headline power savings hinge on unshown timing closure and the accuracy claim lacks classification numbers. read the letter →

arxiv 2505.23553 v1 pith:ZRHSOKUS submitted 2025-05-29 cs.AR

Georgios Alexandris , Panagiotis Chaidos , Alexis Maras , Barry de Bruin , Manil Dev Gomony , Henk Corporaal , Dimitrios Soudris , Sotirios Xydis This is my paper · ORCID

classification cs.AR

keywords approximatecomputingCGRAvoltageislandDRUMmultiplierenergyefficiencyneuralnetworkmappingMobileNetV2edgeAI

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper is trying to show that a coarse-grained reconfigurable array (CGRA) can become much more energy-efficient without losing programmability or accuracy. The authors extend the R-Blocks CGRA with DRUM approximate multipliers and decide which neural-network output channels use them by ranking channels with an importance factor under a user-set quality-of-service constraint. Since the approximate multipliers have shorter critical paths than accurate ones, the framework places them, together with ALUs, register files, and nearby switchboxes, in a 0.6 V voltage island while the rest of the chip stays at 0.8 V. Across the evaluated designs the paper reports an average 30% power reduction with less than 2% area overhead, reaching up to 440 GOPS/W on MobileNetV2 over ImageNet. If the timing of the low-voltage island holds, this would make approximate CGRAs a practical edge-AI option that approaches ASIC efficiency while remaining reconfigurable.

What carries the argument

The central machinery is threefold. First, the DRUM approximate multiplier, which captures the leading-one position of each operand, multiplies only the following $k$ bits with an accurate $k\times k$ multiplier, sets the captured LSB to 1 for unbiasing, and then shifts the result back; its shorter path is what makes voltage scaling possible. Second, the importance factor $I_{oc,l} = \mathrm{MSE}(Q_{out}(D,W), Q_{ax}(D,W,oc,l))$, which measures how much approximating the multiplications of output channel $oc$ in layer $l$ changes the output feature map, and the mapping rule that consumes the least important channels first until the QoS threshold $\alpha$ is met. Third, static voltage-island formation through UPF, which places approximate multipliers, ALUs, register files, and their switchboxes in a 0.6 V domain and the rest at 0.8 V, reducing the timing slack deviation among tiles from 300 ps to 104 ps. Together these let the framework co-optimize mapping and hardware instead of treating approximation and power as separate decisions.

What would settle it

Run post-synthesis static timing analysis on the 0.6 V domain at 400 MHz: if any register-to-register path in that island violates the clock period, the reported power numbers do not describe a valid design. Independently, measure top-1/top-5 ImageNet accuracy for each quantile mapping instead of relying on RMSE; if classification accuracy collapses despite RMSE in the 5.4–6.2 range, the quality proxy used in the paper would be shown inadequate.

Watch

Extended reading notes

Core claim

The paper's central claim is that a heterogeneous CGRA pairing accurate multipliers with DRUM approximate multipliers, and then dropping the supply voltage of the approximate region to 0.6 V, is valid and substantially more efficient than the iso-resource R-Blocks baseline. The argument runs at two levels: the approximate units' shorter critical paths leave slack that can be traded for voltage, and a per-output-channel importance score—computed as the squared change in the output feature map when that channel's multiplications are approximated—tells the mapper which channels can safely run on approximate hardware under a QoS threshold. On scalar, Vector-4, and Vector-8 architectures the measured power savings are 6%, 32.6%, and 29.3% respectively, with less than 2% area overhead, and the reported energy efficiency reaches 378–440 GOPS/W on MobileNetV2. The same flow, from high-level model to synthesizable RTL, is what makes this co-optimization practical.

Load-bearing premise

The 30% power saving rests on the unverified premise that the 0.6 V island containing the DRUM multipliers, ALUs, register files, and connected switchboxes still meets the 400 MHz clock constraint after synthesis; the paper reports slack deviations but no post-voltage-scaling timing-closure data.

Editorial extensions

If this is right

Vectorized CGRA designs can expect roughly 30% power savings from this approach at a 2% area cost, while scalar designs gain little because they contain only one approximate multiplier.
A designer can trade accuracy for energy in fine steps by setting the QoS quantile threshold, with the 0.5 quantile (roughly half the channels approximate) giving a balanced operating point.
Because the voltage islands are defined in standard UPF and the mapping uses standard compiler intrinsics, the technique can be applied to other CGRA templates that support heterogeneous PEs.
The reported 378–440 GOPS/W on MobileNetV2 places the generated architectures ahead of several published CGRA accelerators in throughput and energy efficiency.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The importance-factor mapping is not tied to DRUM specifically: any approximate multiplier with a shorter critical path and a known error model could be dropped into the same per-channel mapping flow, so the framework likely generalizes to other approximate arithmetic families.
The paper reports output RMSE rather than top-1/top-5 accuracy, so a natural next experiment is to fine-tune or retrain the model with the approximate units in the loop; this could either confirm that RMSE in the 5.4–6.2 range is a faithful proxy or reveal a gap.
The static voltage-island choice is justified by low tile-utilization variance on DNN workloads; for multi-tenant or input-dependent workloads with higher variance, a hybrid static-plus-dynamic voltage scheme could extend the savings, though the paper does not evaluate that.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The short version: this paper proposes a per-output-channel importance-based mapping of DNN convolutions onto approximate DRUM multipliers in an R-Blocks CGRA, plus static voltage islands, and reports an average 30% power reduction for two vectorized designs at 2% area overhead. The components are known, but the integration is new and the engineering is plausible. That said, the headline claim rests on timing closure of a 0.6V voltage island that is asserted but not demonstrated, and the accuracy story is built on output RMSE rather than ImageNet classification accuracy.

What's genuinely new: the per-channel importance factor (adapted from Taylor-based pruning) that decides which output channels go to approximate multipliers, and the voltage island formation that groups approximate multipliers, ALUs, register files, and switchboxes in a low-voltage domain. The full C-to-RTL flow is a nice contribution. The paper is clearly written and the related work table is useful.

What it does well: the synthesis flow is standard and the power/area numbers for the vectorized designs are credible if the voltage domains close timing. The use of UPF for voltage islands is appropriate. The scalar architecture showing only 6% saving is a sensible sanity check.

Where it's soft: the paper never shows a post-voltage-scaling STA report for the 0.6V domain. It reports slack deviation dropping from 300ps to 104ps, but that's not a timing closure check. DRUM7 at 0.8V has a 932ps delay, and near-threshold operation can multiply delay by 2-3x. The ALUs and switchboxes in that domain may not have the same slack. If the 0.6V domain misses 400MHz, the design runs slower or at a higher voltage, and the 30% figure needs to be re-derived. This is an evidence gap, not a proven error, but it's load-bearing.

Second, the paper claims "without compromising model accuracy" but reports only output RMSE (5.4-6.2 on MobileNetV2). RMSE is not classification accuracy. The authors need top-1/top-5 numbers. Third, Table III is non-monotonic: the 0.5 quantile has fewer cycles than 0.25 or 0.75, which is unexplained and may indicate a mapping artifact or a typo. Fourth, the SOTA comparison claims "up to 440 GOPS/W" and outperforming X-CGRA, GREEN, etc., but no numeric comparison table is provided.

The mapping strategy validation has a mild circularity: importance factors are computed on the same data used to report RMSE. That's a minor issue because the power savings are physical, not fitted.

Overall, the idea is worth serious consideration. A solid referee could help by requesting the missing timing data and accuracy numbers. I'd send it to review, but with a clear request for major revisions.

Referee Report

3 major / 5 minor

Summary. This paper presents an end-to-end framework for introducing approximate DRUM multipliers into the R-Blocks CGRA, mapping DNN output channels to approximate or accurate multipliers based on per-channel importance factors, and forming static voltage islands at 0.6 V and 0.8 V using UPF. The authors evaluate three R-Blocks variants (Scalar, Vector-4, Vector-8) on MobileNetV2/ImageNet, reporting output-feature RMSE, area, power, and throughput. The headline claims are an average 30% power/energy reduction versus the baseline with a 2% area overhead, and up to 440 GOPS/W.

Significance. If the claims hold, the framework is a useful contribution: it combines approximate arithmetic, static voltage-island formation, and QoS-driven per-channel mapping in a single C-to-RTL flow, and it reports physical-design measurements (synthesis at 22 nm, real SRAM macros, SAIF-based PrimeTime power) rather than only architectural estimates. The inclusion of memory components in area and power, unlike some prior CGRA studies, makes the comparison more credible. The main limitations are evidentiary: timing closure of the low-voltage island is asserted but not demonstrated, and model quality is reported as output RMSE rather than ImageNet classification accuracy. Both are fixable with additional measurements and analysis.

major comments (3)

[III-D] The claim that reducing the operating voltage of the approximate tiles to 0.6 V "ensures that no timing violations occur" is not supported by the reported evidence. The only timing statistic given, a reduction of slack deviation from 300 ps to 104 ps, is a dispersion measure, not a setup- or hold-time closure check. Since DRUM7 at 0.8 V has a delay of 932 ps (Table II) and near-threshold voltage scaling can increase delays by 2-3x or more, the ALUs, register files, and switchboxes in the 0.6 V domain may not meet the 400 MHz (2.5 ns) clock constraint. Please report post-scaling critical-path delays, setup and hold slack for the 0.6 V domain, and the delay at 0.6 V for each component in the island; otherwise the 29-33% power reductions in Figure 4b do not describe a valid operating point.
[V-B] The paper's accuracy-related claims are not substantiated by the reported metric. Table III reports output-feature RMSE values of 5.4-6.2, but the abstract and introduction claim the method "retains accuracy" and "does not compromise model accuracy" (Section I). RMSE of output features is not a substitute for top-1/top-5 classification accuracy on ImageNet, especially when approximate multipliers are applied per channel according to Eq. (1). Please report ImageNet top-1 and top-5 accuracy for the quantile mappings in Table III, or at least provide a correlation study between RMSE and accuracy for a subset of configurations.
[IV-B/V-B] The validation of the mapping strategy is potentially circular. Eq. (1) computes importance factors I_oc,l by measuring the sensitivity of output feature maps Qout on a dataset D to approximate multiplication on each channel; Section V-B then reports output RMSE on what appears to be the same ImageNet inference pass. If D is the same data used both to choose the per-channel mapping and to compute the reported RMSE, the error numbers in Table III reflect an in-sample fit rather than generalization. Please specify how ImageNet is split into importance-estimation and evaluation sets, and report RMSE (and accuracy) on an evaluation set that was not used to compute the importance factors.

minor comments (5)

[Abstract/V-C] The abstract states "reduction in energy consumption" while the results measure power at a fixed clock; since frequency is unchanged, energy per operation scales with power, but the terminology should be aligned throughout the paper.
[Table III] The table header "OC map (%) Quantile Perf (CC) RMSE Acc Ax" is ambiguous; the Acc and Ax columns list percentages of accurate and approximate channels but are never defined in the caption, and the first column appears to be the quantile, not a percentage map. Please rename and clarify.
[III-D] The source of the 300 ps-to-104 ps slack-deviation figures is not described; please state how slack was measured per tile, at which voltage, and whether these are pre- or post-layout numbers.
[V-C] Figure 4b shows only a 6% power reduction for the scalar architecture; a short analysis of why the scalar design does not benefit would help, beyond the count of approximate multipliers.
[Throughout] There are several typos and formatting issues, including "i.e,", "false,,", "V oltage", and "SOtA"; the manuscript should be carefully proofread.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central power, area, and error results come from independent synthesis, UPF-based voltage islands, and direct DRUM multiplier modeling, not from parameters fitted to the headline claims.

full rationale

The paper's main claims are grounded in external, independently reproducible components: DRUM multiplier PPA numbers (Table II) are obtained from Synopsys Design Compiler at 22 nm and 0.8 V; the power comparisons in Figure 4b come from post-synthesis SAIF-based PrimeTime analysis of Verilog netlists with UPF-defined voltage domains; and the accuracy analysis uses a Brevitas-based DRUM simulation extended from an external library. The per-channel importance factors in Eq. (1) are defined as the measured output MSE when approximating one channel, and the mapping strategy then chooses which channels to approximate. The reported Table III output RMSE values are measurements of the resulting architecture on the same ImageNet data used for importance computation. This is an in-sample evaluation concern and a generalization risk, but it is not circularity: the final RMSE is a measured outcome of the selected mapping, not the same quantity as the per-channel importance factors, and no equation reduces the reported result to its own input by construction. Self-citations to R-Blocks [12] and to OpenASIP [19] provide baseline architectures and compiler infrastructure; they are external prior works with independent content, and no load-bearing argument reduces to an unverified self-citation. The absence of post-voltage-scaling timing closure reports is a correctness/support gap, not a circular derivation. Overall, the derivation chain is self-contained with respect to circularity, and the score reflects that finding.

Assumptions & free parameters 3 free parameters · 6 assumptions · 0 invented entities

The paper introduces no new physical entities; its contributions are a combination of existing components. The list above captures the premises the central claims rest on: the DRUM LUT model, the importance-sensitivity assumption, the RMSE proxy, voltage-domain timing closure, the R-Blocks baseline, and the compiler correctness.

free parameters (3)

Low voltage domain value = 0.6 V
Chosen by hand as the reduced voltage for approximate multipliers, ALUs, register files, and adjacent switchboxes; it directly determines the power savings and must still close timing.
DRUM configuration k = 7
The DRUM multiplier size is set to k=7 for the MobileNetV2 experiments; Table II shows k=4..6 have different error/power trade-offs, and no DNN experiments are reported for other k.
QoS quantile threshold alpha = 0.5 (highlighted)
The user-defined constraint that determines how many output channels are mapped to approximate multipliers; the paper sweeps quantiles and highlights 0.5 as giving the best cycle count, but no external accuracy target is used to set it.

assumptions (6)

domain assumption DRUM approximate multiplier behavior, as specified in Hashemi et al. [15], is accurately captured by the LUTs used in the Brevitas extension.
Section IV-A states that approximate units are simulated via LUTs storing all possible N x N multiplications; this assumes the LUT model exactly matches the synthesized DRUM hardware.
domain assumption The importance estimation framework of Molchanov et al. [27], adapted from pruning, produces an ordering of output channels that is meaningful for approximating rather than removing them.
Section IV-B adapts the Taylor-based importance score; this assumes the same first-order sensitivity metric is valid for assigning channels to approximate multipliers.
ad hoc to paper Output feature RMSE is an acceptable proxy for DNN inference quality.
Table III and the abstract use RMSE (5.4-6.2) as the sole quality metric; no ImageNet classification accuracy is reported, so this assumption carries the accuracy claim.
domain assumption Voltage scaling reduces power and increases delay monotonically, and the 0.6V domain closes timing at 400 MHz.
Section III-D claims no timing violations from voltage reduction based on slack; no post-scaling delay reports are shown.
domain assumption The R-Blocks baseline [12] is a valid and representative CGRA to extend.
The comparisons in Section V-C use iso-resource R-Blocks designs as baseline; the paper relies on the R-Blocks microarchitecture and compiler being correct.
domain assumption The TTA-based compilation flow and iterative pruning preserve program semantics and schedulability.
Section III-B relies on the OpenASIP compiler and the Pruner to maintain correctness; no formal verification or exhaustive testing is described.

how reviews work

0 comments

Cite this review

Pith. "Pith review of A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs." pith.science (2026). https://pith.science/paper/ZRHSOKUS

@misc{pith2026250523553,
  author       = {Pith},
  title        = {Pith review of: A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZRHSOKUS}},
  note         = {Machine review of arXiv:2505.23553}
}

read the original abstract

The ever-increasing complexity and operational diversity of modern Neural Networks (NNs) have caused the need for low-power and, at the same time, high-performance edge devices for AI applications. Coarse Grained Reconfigurable Architectures (CGRAs) form a promising design paradigm to address these challenges, delivering a close-to-ASIC performance while allowing for hardware programmability. In this paper, we introduce a novel end-to-end exploration and synthesis framework for approximate CGRA processors that enables transparent and optimized integration and mapping of state-of-the-art approximate multiplication components into CGRAs. Our methodology introduces a per-channel exploration strategy that maps specific output features onto approximate components based on accuracy degradation constraints. This enables the optimization of the system's energy consumption while retaining the accuracy above a certain threshold. At the circuit level, the integration of approximate components enables the creation of voltage islands that operate at reduced voltage levels, which is attributed to their inherently shorter critical paths. This key enabler allows us to effectively reduce the overall power consumption by an average of 30% across our analyzed architectures, compared to their baseline counterparts, while incurring only a minimal 2% area overhead. The proposed methodology was evaluated on a widely used NN model, MobileNetV2, on the ImageNet dataset, demonstrating that the generated architectures can deliver up to 440 GOPS/W with relatively small output error during inference, outperforming several State-of-the-Art CGRA architectures in terms of throughput and energy efficiency.

Figures

Figures reproduced from arXiv: 2505.23553 by the authors.

**Figure 2.** SW Compilation & HW Generation Flow architectural model of the target CGRA, thus, it performs operation scheduling under relaxed inter-tile connectivity constraints. This high-level fully-connected micro-architectural model is then iteratively refined to fit the connectivity constraints imposed by the 2D-mesh programmable NoC. An iterative pruning process is employed, i.e., the Pruner ( [PITH_FULL_IMAGE:figures/f… view at source ↗

**Figure 3.** Overview of the proposed DNN mapping flow. For each conv layer, the process begins by extracting the importance [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: Area and power comparison of the examined ar [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

28 extracted references · 18 canonical work pages

[1]

Empowering edge intelligence: A comprehensive survey on on-device ai models,

X. Wang, Z. Tang, J. Guo, T. Meng, C. Wang, T. Wang, and W. Jia, “Empowering edge intelligence: A comprehensive survey on on-device ai models,” ACM Comput. Surv. , Mar. 2025, just Accepted. [Online]. Available: https://doi.org/10.1145/3724420

doi:10.1145/3724420 2025
[2]

An evaluation of edge tpu accelerators for convolutional neural networks,

K. Seshadri, B. Akin, J. Laudon, R. Narayanaswami, and A. Yazdanbakhsh, “An evaluation of edge tpu accelerators for convolutional neural networks,” 2022. [Online]. Available: https://arxiv.org/abs/2102.10423

arXiv 2022
[3]

Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,

H. Genc, S. Kim, A. Amid, A. Haj-Ali, V . Iyer, P. Prakash, J. Zhao, D. Grubb, H. Liew, H. Mao, A. Ou, C. Schmidt, S. Steffl, J. Wright, I. Stoica, J. Ragan-Kelley, K. Asanovic, B. Nikolic, and Y . S. Shao, “Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,” in 2021 58th ACM/IEEE Design Automation Conference (D...

arXiv 2021
[4]

X-CGRA: An Energy-Efficient Approximate Coarse- Grained Reconfigurable Architecture,

O. Akbari, M. Kamal, A. Afzali-Kusha, M. Pedram, and M. Shafique, “X-CGRA: An Energy-Efficient Approximate Coarse- Grained Reconfigurable Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 10, pp. 2558–2571, Oct. 2020. [Online]. Available: https://ieeexplore.ieee.org/document/8815818/

work page arXiv 2020
[5]

GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge,

Z. Ebrahimi and A. Kumar, “GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 43, no. 10, pp. 2874–2887, Oct. 2024. [Online]. Available: https://ieeexplore.ieee.org/document/10488043/

work page arXiv 2024
[6]

Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications,

M. Brandalero, L. Carro, A. C. S. Beck, and M. Shafique, “Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications,” in Proceedings of the 55th Annual Design Automation Conference , ser. DAC ’18. New York, NY , USA: Association for Computing Machinery, 2018. [Online]. Available: https://doi.org/10.1145/3195970.3195993

work page arXiv 2018
[7]

Cgra-me: A unified framework for cgra modelling and exploration,

S. A. Chin, N. Sakamoto, A. Rui, J. Zhao, J. H. Kim, Y . Hara- Azumi, and J. Anderson, “Cgra-me: A unified framework for cgra modelling and exploration,” in 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) , 2017, pp. 184–189

work page 2017
[8]

Revamp: a systematic framework for heterogeneous cgra realization,

T. K. Bandara, D. Wijerathne, T. Mitra, and L.-S. Peh, “Revamp: a systematic framework for heterogeneous cgra realization,” in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ’22. New York, NY , USA: Association for Computing Machinery, 2022, p. 918–932. [Online]. A...

arXiv 2022

Show all 28 references

[9]

Cgra4ml: A framework to implement modern neural networks for scientific edge computing,

G. Abarajithan, Z. Ma, Z. Li, S. Koparkar, R. Munasinghe, F. Restuccia, and R. Kastner, “Cgra4ml: A framework to implement modern neural networks for scientific edge computing,” 2024. [Online]. Available: https://arxiv.org/abs/2408.15561

2024
[10]

Ml-cgra: An integrated compilation framework to enable efficient ma- chine learning acceleration on cgras,

Y . Luo, C. Tan, N. B. Agostini, A. Li, A. Tumeo, N. Dave, and T. Geng, “Ml-cgra: An integrated compilation framework to enable efficient ma- chine learning acceleration on cgras,” in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1–6

2023
[11]

Iced: An integrated cgra framework enabling dvfs-aware acceleration,

C. Tan, M. Jiang, D. Patil, Y . Ou, Z. Li, L. Ju, T. Mitra, H. Park, A. Tumeo, and J. Zhang, “Iced: An integrated cgra framework enabling dvfs-aware acceleration,” in 2024 57th IEEE/ACM International Sym- posium on Microarchitecture (MICRO) , 2024, pp. 1338–1352

2024
[12]

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA,

B. De Bruin, K. Vadivel, M. Wijtvliet, P. J ¨a¨askel¨ainen, and H. Corporaal, “R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA,” ACM Transactions on Reconfigurable Technology and Systems , vol. 17, no. 2, pp. 1–34, Jun. 2024. [Online]. Available: https://dl.acm....

2024 doi
[13]

Coarse grained reconfig- urable architectures in the past 25 years: Overview and classification,

M. Wijtvliet, L. Waeijen, and H. Corporaal, “Coarse grained reconfig- urable architectures in the past 25 years: Overview and classification,” in 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) , 2016, pp. 235–244

2016
[14]

Opencgra: An open- source unified framework for modeling, testing, and evaluating cgras,

C. Tan, C. Xie, A. Li, K. J. Barker, and A. Tumeo, “Opencgra: An open- source unified framework for modeling, testing, and evaluating cgras,” in 2020 IEEE 38th International Conference on Computer Design (ICCD) , 2020, pp. 381–388

2020
[15]

DRUM: A Dynamic Range Unbiased Multiplier for approximate applications,

S. Hashemi, R. I. Bahar, and S. Reda, “DRUM: A Dynamic Range Unbiased Multiplier for approximate applications,” in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Austin, TX, USA: IEEE, Nov. 2015, pp. 418–425. [Online]. Available: http://ieeexplore.iee...

2015
[16]

Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect,

M. Karunaratne, A. K. Mohite, T. Mitra, and L.-S. Peh, “Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect,” in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, pp. 1–6

2017
[17]

Mlir: A compiler infrastructure for the end of moore’s law,

C. Lattner, M. Amini, U. Bondhugula, A. Cohen, A. Davis, J. Pienaar, R. Riddle, T. Shpeisman, N. Vasilache, and O. Zinenko, “Mlir: A compiler infrastructure for the end of moore’s law,” 2020. [Online]. Available: https://arxiv.org/abs/2002.11054

2020 arXiv
[18]

A tileable switch module architecture for homogeneous 3d fpgas,

S. A. Razavi, M. S. Zamani, and K. Bazargan, “A tileable switch module architecture for homogeneous 3d fpgas,” in 2009 IEEE International Conference on 3D System Integration , 2009, pp. 1–4

2009
[19]

Hw/sw co-design toolset for customization of exposed datapath processors,

P. J ¨a¨askel¨ainen, T. Viitanen, J. Takala, and H. Berg, “Hw/sw co-design toolset for customization of exposed datapath processors,” Computing platforms for software-defined radio , pp. 147–164, 2017

2017
[20]

Tta processor synthesis,

H. Corporaal and R. Lamberts, “Tta processor synthesis,” in First Annual Conf. of ASCI . Citeseer, 1995, pp. 18–27

1995
[21]

Walking through the energy-error pareto frontier of approximate multipliers,

V . Leon, G. Zervakis, S. Xydis, D. Soudris, and K. Pekmestzi, “Walking through the energy-error pareto frontier of approximate multipliers,” IEEE Micro, vol. 38, no. 4, pp. 40–49, 2018

2018
[22]

Cooperative arithmetic-aware approximation techniques for energy- efficient multipliers,

V . Leon, K. Asimakopoulos, S. Xydis, D. Soudris, and K. Pekmestzi, “Cooperative arithmetic-aware approximation techniques for energy- efficient multipliers,” in Proceedings of the 56th Annual Design Automation Conference 2019 , ser. DAC ’19. New York, NY , USA: Association fo...

2019
[23]

Approximate arithmetic circuits: A survey, characterization, and recent applications,

H. Jiang, F. J. H. Santiago, H. Mo, L. Liu, and J. Han, “Approximate arithmetic circuits: A survey, characterization, and recent applications,” Proceedings of the IEEE , vol. 108, no. 12, pp. 2108–2135, 2020

2020
[24]

A survey on approximate multiplier designs for energy efficiency: From algorithms to circuits,

Y . Wu, C. Chen, W. Xiao, X. Wang, C. Wen, J. Han, X. Yin, W. Qian, and C. Zhuo, “A survey on approximate multiplier designs for energy efficiency: From algorithms to circuits,” ACM Trans. Des. Autom. Electron. Syst. , vol. 29, no. 1, Jan. 2024. [Online]. Available: https://do...

2024 doi
[25]

Fine-grained power and body-bias control for near-threshold deep sub-micron cmos circuits,

M. R. Kakoee and L. Benini, “Fine-grained power and body-bias control for near-threshold deep sub-micron cmos circuits,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems , vol. 1, no. 2, pp. 131–140, 2011

2011
[26]

Brevitas,

AMD-Xilinx, “Brevitas,” https://github.com/Xilinx/brevitas
[27]

Importance Estimation for Neural Network Pruning,

P. Molchanov, A. Mallya, S. Tyree, I. Frosio, and J. Kautz, “Importance Estimation for Neural Network Pruning,” Jun. 2019, arXiv:1906.10771 [cs]. [Online]. Available: http://arxiv.org/abs/1906.10771

2019 arXiv
[28]

Imagenet: A large-scale hierarchical image database,

J. Deng, W. Dong, R. Socher, L.-J. Li, K. Li, and L. Fei-Fei, “Imagenet: A large-scale hierarchical image database,” in 2009 IEEE Conference on Computer Vision and Pattern Recognition , 2009, pp. 248–255

2009

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

Empowering edge intelligence: A comprehensive survey on on-device ai models,

X. Wang, Z. Tang, J. Guo, T. Meng, C. Wang, T. Wang, and W. Jia, “Empowering edge intelligence: A comprehensive survey on on-device ai models,” ACM Comput. Surv. , Mar. 2025, just Accepted. [Online]. Available: https://doi.org/10.1145/3724420

doi:10.1145/3724420 2025

[2] [2]

An evaluation of edge tpu accelerators for convolutional neural networks,

K. Seshadri, B. Akin, J. Laudon, R. Narayanaswami, and A. Yazdanbakhsh, “An evaluation of edge tpu accelerators for convolutional neural networks,” 2022. [Online]. Available: https://arxiv.org/abs/2102.10423

arXiv 2022

[3] [3]

Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,

H. Genc, S. Kim, A. Amid, A. Haj-Ali, V . Iyer, P. Prakash, J. Zhao, D. Grubb, H. Liew, H. Mao, A. Ou, C. Schmidt, S. Steffl, J. Wright, I. Stoica, J. Ragan-Kelley, K. Asanovic, B. Nikolic, and Y . S. Shao, “Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration,” in 2021 58th ACM/IEEE Design Automation Conference (D...

arXiv 2021

[4] [4]

X-CGRA: An Energy-Efficient Approximate Coarse- Grained Reconfigurable Architecture,

O. Akbari, M. Kamal, A. Afzali-Kusha, M. Pedram, and M. Shafique, “X-CGRA: An Energy-Efficient Approximate Coarse- Grained Reconfigurable Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 10, pp. 2558–2571, Oct. 2020. [Online]. Available: https://ieeexplore.ieee.org/document/8815818/

work page arXiv 2020

[5] [5]

GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge,

Z. Ebrahimi and A. Kumar, “GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 43, no. 10, pp. 2874–2887, Oct. 2024. [Online]. Available: https://ieeexplore.ieee.org/document/10488043/

work page arXiv 2024

[6] [6]

Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications,

M. Brandalero, L. Carro, A. C. S. Beck, and M. Shafique, “Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications,” in Proceedings of the 55th Annual Design Automation Conference , ser. DAC ’18. New York, NY , USA: Association for Computing Machinery, 2018. [Online]. Available: https://doi.org/10.1145/3195970.3195993

work page arXiv 2018

[7] [7]

Cgra-me: A unified framework for cgra modelling and exploration,

S. A. Chin, N. Sakamoto, A. Rui, J. Zhao, J. H. Kim, Y . Hara- Azumi, and J. Anderson, “Cgra-me: A unified framework for cgra modelling and exploration,” in 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) , 2017, pp. 184–189

work page 2017

[8] [8]

Revamp: a systematic framework for heterogeneous cgra realization,

T. K. Bandara, D. Wijerathne, T. Mitra, and L.-S. Peh, “Revamp: a systematic framework for heterogeneous cgra realization,” in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ’22. New York, NY , USA: Association for Computing Machinery, 2022, p. 918–932. [Online]. A...

arXiv 2022