Paper Citation Record · LEDGER

Large Processor Chip Model

As of 23 August 2026, this Paper Citation Record lists 45 of 45 outbound references and 1 inbound Pith citation observation for arXiv:2506.02929.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.02929 v1

Coverage vector

measured 45 of 45 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T11:16:43.526221Z

measured 46 of 46 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-22T06:32:14.747728+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-04T16:31:32.400161Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

45 of 45 outbound references displayed

verified exact1
verified fuzzy33
unresolved11
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 4952442d-5b35-4c7d-967a-826b9e8fb901 · outbound

This paper cites A new golden age for computer architecture.

Large Processor Chip Model A new golden age for computer architecture

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.909558Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 2033b638-70ab-40c4-814a-f954a94de50b · outbound

This paper cites Dagon: Technology binding and local optimization by dag matching.

Large Processor Chip Model Dagon: Technology binding and local optimization by dag matching

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.598050Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 1efcae57-5a48-4b53-8288-8174b3c25b30 · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

Large Processor Chip Model ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:39.900583Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 51d3019d-ba4d-4e79-918d-08e6ac28b821 · outbound

This paper cites Divide-and-conquer approach for multi-phase statistical migration for source code (t).

Large Processor Chip Model Divide-and-conquer approach for multi-phase statistical migration for source code (t)

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.647487Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 35c4a4eb-7d19-4ca9-848d-6e2ada459473 · outbound

This paper cites Refining Decompiled C Code with Large Language Models.

Large Processor Chip Model Refining Decompiled C Code with Large Language Models

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:40.600977Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e6940d76-e795-4789-bd95-70759568382d · outbound

This paper cites 03152 44 Jiang N, Becker D U, Michelogiannakis G, et al.

Large Processor Chip Model 03152 44 Jiang N, Becker D U, Michelogiannakis G, et al

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.325669Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0323a472-4c15-4190-9877-2320cf600cfd · outbound

This paper cites Simulated annealing.

Large Processor Chip Model Simulated annealing

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:47.659559Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0186b98f-e710-459a-b8e6-64d1b9060946 · outbound

This paper cites A High-accurate Multi-objective Exploration Framework for Design Space of CPU.

Large Processor Chip Model A High-accurate Multi-objective Exploration Framework for Design Space of CPU

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:47.328264Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 4477f2a6-d206-4abe-af0f-5e0d934c315f · outbound

This paper cites Accurate and efficient regression modeling for microarchitectural performance and power prediction.

Large Processor Chip Model Accurate and efficient regression modeling for microarchitectural performance and power prediction

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:47.132629Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 35102492-30b8-4151-bdae-f25b84ebdc8d · outbound

This paper cites ArchRanker: A ranking approach to design space exploration.

Large Processor Chip Model ArchRanker: A ranking approach to design space exploration

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:46.956774Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation e1bee1d5-79c1-4c0a-b678-5430dc6483cb · outbound

This paper cites McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.

Large Processor Chip Model McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:46.744348Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 9a1d2670-e0a5-4b23-9734-90125c2fe262 · outbound

This paper cites Cross-program design space exploration by ensemble transfer learning.

Large Processor Chip Model Cross-program design space exploration by ensemble transfer learning

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:46.345185Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation ffd23136-ff41-49d3-830c-498266d8407f · outbound

This paper cites A transfer learning framework for high-accurate cross-workload design space exploration of cpu.

Large Processor Chip Model A transfer learning framework for high-accurate cross-workload design space exploration of cpu

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:45.998171Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 97752ecd-190f-4457-a730-29ab1473f0a0 · outbound

This paper cites Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.

Large Processor Chip Model Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:45.777612Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation ce1777a7-b22b-401d-9695-17d7c9b2deab · outbound

This paper cites Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.

Large Processor Chip Model Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:45.539934Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation d80d07dc-cd27-490a-a726-7d50c27a9957 · outbound

This paper cites Design-Space Exploration and Runtime Resource Management for Multicores.

Large Processor Chip Model Design-Space Exploration and Runtime Resource Management for Multicores

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:45.278545Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 59f8e148-8679-4622-b0f4-e7ab2923b639 · outbound

This paper cites OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.

Large Processor Chip Model OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:44.703351Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 62c6605e-f9b2-4429-8735-969f5fc32e9b · outbound

This paper cites Polysa: Polyhedral-based systolic array auto-compilation.

Large Processor Chip Model Polysa: Polyhedral-based systolic array auto-compilation

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:44.549371Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation a10bd3bc-721a-4ca1-b1f2-54b51487772b · outbound

This paper cites Autosa: A polyhedral compiler for high-performance systolic arrays on fpga.

Large Processor Chip Model Autosa: A polyhedral compiler for high-performance systolic arrays on fpga

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:44.390960Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation a8460e10-8da9-4eca-8dca-e0a39bf8ecbe · outbound

This paper cites Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures.

Large Processor Chip Model Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:44.187472Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 0dca02c5-1c6d-45a4-8114-172671b8896e · outbound

This paper cites URL https://doi.org/10.1109/MLCAD58807.2023.10299874 87 Thakur S, Blocklove J, Pearce H, et al.

Large Processor Chip Model URL https://doi.org/10.1109/MLCAD58807.2023.10299874 87 Thakur S, Blocklove J, Pearce H, et al

Reference 41

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:43.170716Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ceb51950-3fe7-46c0-a3c3-e23d1a137490 · outbound

This paper cites Co-designing accelerators and soc interfaces using gem5-aladdin.

Large Processor Chip Model Co-designing accelerators and soc interfaces using gem5-aladdin

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.018249Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation cca114fa-e0e2-4ad7-a104-baf881aa16f8 · outbound

This paper cites URL https://doi.org/10.23919/DATE56975.2023.10137086 91 Liu M, Pinckney N R, Khailany B, et al.

Large Processor Chip Model URL https://doi.org/10.23919/DATE56975.2023.10137086 91 Liu M, Pinckney N R, Khailany B, et al

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:43.251774Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 94f066f3-278f-4544-b315-70632e3a5e39 · outbound

This paper cites URL https://doi.org/10.1109/ICCAD57390.2023.10323812 92 Nadimi B, Zheng H.

Large Processor Chip Model URL https://doi.org/10.1109/ICCAD57390.2023.10323812 92 Nadimi B, Zheng H

Reference 44

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:43.340163Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 80562452-0a8a-48ce-a537-d3a08613751d · outbound

This paper cites URL https://doi.org/10.1109/ASP-DAC58780.2024.10473904 95 Wu P, Guo N, Xiao X, et al.

Large Processor Chip Model URL https://doi.org/10.1109/ASP-DAC58780.2024.10473904 95 Wu P, Guo N, Xiao X, et al

Reference 45

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:43.428149Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6d2423c5-1d50-40f7-9950-e7d36abd573f · outbound

This paper cites MAGE: A Multi-Agent Engine for Automated RTL Code Generation.

Large Processor Chip Model MAGE: A Multi-Agent Engine for Automated RTL Code Generation

Reference 46

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:43.526221Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4036a7c5-afb7-4dd8-a090-40f905a4f0c0 · outbound

This paper cites Boils: Bayesian optimisation for logic synthesis.

Large Processor Chip Model Boils: Bayesian optimisation for logic synthesis

Reference 1987

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.450116Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 6fe7c5a6-7cb9-4dfd-866c-cc6672bb8bf8 · outbound

This paper cites Toward an open-source digital flow: First learnings from the openroad project.

Large Processor Chip Model Toward an open-source digital flow: First learnings from the openroad project

Reference 1988

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.114728Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation da145592-5beb-4d70-8a63-a4d7e927640a · outbound

This paper cites Efficient design space exploration via statistical sampling and adaboost learning.

Large Processor Chip Model Efficient design space exploration via statistical sampling and adaboost learning

Reference 2006

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:47.488013Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation ab5a6142-a4ee-4035-b955-804655a6200f · outbound

This paper cites Machine-learning based simulated annealer method for high level synthesis design space explo- ration.

Large Processor Chip Model Machine-learning based simulated annealer method for high level synthesis design space explo- ration

Reference 2009

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.767955Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 470f59a3-7dd5-4d08-bcd8-7ed6949b908f · outbound

This paper cites An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Sci China Inf Sci 32 Architectures based on Artificial Neural Networks.

Large Processor Chip Model An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Sci China Inf Sci 32 Architectures based on Artificial Neural Networks

Reference 2010

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:44.882628Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 07300cf6-ed63-4c01-b237-818ef3181003 · outbound

This paper cites Improving performance estimation for fpga-based accelerators for convolutional neural networks.

Large Processor Chip Model Improving performance estimation for fpga-based accelerators for convolutional neural networks

Reference 2012

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.801624Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 2f8b5102-c0d6-40b5-a409-ddf1874422d7 · outbound

This paper cites Qemu, a fast and portable dynamic translator.

Large Processor Chip Model Qemu, a fast and portable dynamic translator

Reference 2013

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.152341Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 2745c208-6970-49ef-acbc-486debb17b1a · outbound

This paper cites Multi-objective Optimization in CPU Design Space Exploration: Attention is All You Need.

Large Processor Chip Model Multi-objective Optimization in CPU Design Space Exploration: Attention is All You Need

Reference 2014

Resolution: verified exact; local_arxiv, observed 2026-08-07T11:16:43.990653Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 1bd56e34-81a4-493d-8f76-d78d50f9d839 · outbound

This paper cites Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.

Large Processor Chip Model Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors

Reference 2015

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:45.089316Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 22e1fb72-11a6-4a98-a65b-b7f12f61cc61 · outbound

This paper cites System level hardware/software partitioning based on simulated annealing and tabu search.

Large Processor Chip Model System level hardware/software partitioning based on simulated annealing and tabu search

Reference 2016

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:47.832291Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation db459ea2-1e5f-464d-af8f-8cdf328ba438 · outbound

This paper cites Generative and multi-phase learning for computer systems optimization.

Large Processor Chip Model Generative and multi-phase learning for computer systems optimization

Reference 2017

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:46.171524Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 8ee7ec07-bba4-4bff-bdbf-a7368c766fd0 · outbound

This paper cites Codebert: A pre-trained model for programming and natural languages, 2020 31 Wang Y, Wang W, Joty S, et al.

Large Processor Chip Model Codebert: A pre-trained model for programming and natural languages, 2020 31 Wang Y, Wang W, Joty S, et al

Reference 2018

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.472507Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 93a4eb69-b33b-4389-a03a-1e350b08548c · outbound

This paper cites Machine learning predictive modelling high-level synthesis design space exploration.

Large Processor Chip Model Machine learning predictive modelling high-level synthesis design space exploration

Reference 2019

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:48.949707Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 71e3f2e7-f958-41fc-827c-003a25d87332 · outbound

This paper cites Chip Placement with Deep Reinforcement Learning.

Large Processor Chip Model Chip Placement with Deep Reinforcement Learning

Reference 2020

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:39.817119Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 79acd4d4-4e9b-4df9-bfdb-77c7737a2464 · outbound

This paper cites Learning C to x86 Translation: An Experiment in Neural Compilation.

Large Processor Chip Model Learning C to x86 Translation: An Experiment in Neural Compilation

Reference 2021

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:40.434809Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b1b3095f-4246-4396-92c1-779830c7fe21 · outbound

This paper cites Replace: Advancing solution quality and routability validation in global placement.

Large Processor Chip Model Replace: Advancing solution quality and routability validation in global placement

Reference 2022

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:49.286603Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 9bb6afa4-4075-43b4-9a44-d4407d46b8dc · outbound

This paper cites Efficient design space exploration by knowledge transfer.

Large Processor Chip Model Efficient design space exploration by knowledge transfer

Reference 2023

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T11:16:46.540864Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.

Observation 5a24b38c-d34a-4a90-8010-7af29be36edc · outbound

This paper cites Chateda: A large language model powered autonomous agent for eda.

Large Processor Chip Model Chateda: A large language model powered autonomous agent for eda

Reference 2024

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:40.006065Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cd7f13fb-ae3b-4f71-b4e5-e69b1e60aaf6 · outbound

This paper cites DeepSeek-V3 Technical Report.

Large Processor Chip Model DeepSeek-V3 Technical Report

Reference 2025

Resolution: unresolved; no resolver link, observed 2026-08-07T11:16:41.029803Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

Observation 70a867f6-9ee8-422b-8afe-a8f6b2dd9647 · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design Large Processor Chip Model

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.400161Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.