Paper Citation Record · LEDGER

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

As of 10 August 2026, this Paper Citation Record lists 59 of 59 outbound references and 1 inbound Pith citation observation for arXiv:2506.07239.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.07239 v2

Coverage vector

measured 59 of 59 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T05:43:47.131973Z

measured 60 of 60 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-05-10T11:43:44.174797Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-10T11:45:21.407360Z

Reference resolution

59 of 59 outbound references displayed

verified exact2
verified fuzzy35
unresolved21
parse uncertain0
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External citation measurements

No source-named external measurement is stored.

Outbound references

Observation ca9604e5-89a3-46ea-be12-ce10b1d8fbae · outbound

This paper cites Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Annotating slack directly on your verilog: Fine-grained rtl timing evaluation for early optimization,

Reference 1

Resolution: metadata mismatch; raw_fallback, observed 2026-08-07T05:43:48.387800Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation c01e3042-2591-4549-8522-fefec9f0779c · outbound

This paper cites Applying gnns to timing estimation at rtl : (invited paper),.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Applying gnns to timing estimation at rtl : (invited paper),

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:44:00.717682Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 29bf98a8-87be-42d4-a755-a9854b413637 · outbound

This paper cites Using graph neural networks for timing esti- mations of rtl intermediate representations,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Using graph neural networks for timing esti- mations of rtl intermediate representations,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:44:00.383102Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation a0839ece-d66f-42d2-abb8-4ef9c0ee9214 · outbound

This paper cites Masterrtl: A pre-synthesis ppa estimation framework for any rtl design,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Masterrtl: A pre-synthesis ppa estimation framework for any rtl design,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:44:00.025452Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation c5d7b5cc-e035-4009-8cc2-f88743ef3d90 · outbound

This paper cites Preplacement net length and timing estimation by customized graph neural network,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Preplacement net length and timing estimation by customized graph neural network,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:59.752970Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d9b70027-2731-4a7d-ab69-899ff4abd19e · outbound

This paper cites Drills: Deep reinforcement learning for logic synthesis,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Drills: Deep reinforcement learning for logic synthesis,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:59.437704Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 9df7a1df-cc91-48dc-99b9-fa7562dd3563 · outbound

This paper cites Exploring logic optimizations with reinforcement learning and graph convolutional network,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Exploring logic optimizations with reinforcement learning and graph convolutional network,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:59.075543Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 98368358-6d6b-4d59-b8d4-346aa6949daa · outbound

This paper cites Rl-guided runtime-constrained heuristic exploration for logic synthesis,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Rl-guided runtime-constrained heuristic exploration for logic synthesis,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:58.784232Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d015317d-9cae-4a20-a01b-60493eb1b23d · outbound

This paper cites Bulls-eye: Active few-shot learning guided logic synthesis,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Bulls-eye: Active few-shot learning guided logic synthesis,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:58.356522Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8b563af6-9d45-47a5-816e-995250eb23fe · outbound

This paper cites Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization

Reference 10

Resolution: verified exact; local_arxiv, observed 2026-08-07T05:43:48.053257Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation fa89036a-12d0-4c6a-b0b2-0c95755b4fc3 · outbound

This paper cites The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:39.792235Z

Source-reported events for the cited work

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Observation cc9738bb-65f3-4a57-9404-f90b21f8ae76 · outbound

This paper cites CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:39.926269Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 80b3ae2a-b8c5-4c08-b79e-b779afd0bffb · outbound

This paper cites Rome was not built in a single step: Hierarchical prompting for llm-based chip design,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Rome was not built in a single step: Hierarchical prompting for llm-based chip design,

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:40.243901Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ab40591d-d683-4c56-bf2c-45a6aee65fe5 · outbound

This paper cites LLM2Vec: Large Language Models Are Secretly Powerful Text Encoders.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code LLM2Vec: Large Language Models Are Secretly Powerful Text Encoders

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:40.436145Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a23c5dfa-1855-4fc8-94f4-4ec6bf34d94b · outbound

This paper cites Beyond decoder-only: Large language models can be good encoders for machine translation,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Beyond decoder-only: Large language models can be good encoders for machine translation,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:57.726282Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4f0311ce-df2e-4d65-bf96-0d11cd65038f · outbound

This paper cites Synopsys rtl architect,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Synopsys rtl architect,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:58.048592Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 625aa1a7-2edf-46b7-bb82-23797d9db8ef · outbound

This paper cites Openabc-d: A large-scale dataset for machine learning guided integrated circuit synthesis,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Openabc-d: A large-scale dataset for machine learning guided integrated circuit synthesis,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:57.337690Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 39f2769b-c1d2-4640-9682-0696f5b6b57e · outbound

This paper cites Xgboost: A scalable tree boosting system,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Xgboost: A scalable tree boosting system,

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:41.181456Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 163317fb-3405-4823-90bb-44b5012327aa · outbound

This paper cites Lightgbm: a highly efficient gradient boosting decision tree,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Lightgbm: a highly efficient gradient boosting decision tree,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:57.009577Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e59c3238-001f-4e2c-84cf-599461a6b5a4 · outbound

This paper cites an unresolved cited work.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Unresolved cited work

Reference 21

Resolution: unresolved; raw_fallback, observed 2026-08-07T05:43:56.639230Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation ecd99a03-d8b1-46c9-aec6-fdbfd2fef180 · outbound

This paper cites A simplr method for routability-driven placement,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code A simplr method for routability-driven placement,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:56.323818Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 6461d995-7aaa-46f2-bb4c-31dc58271bfd · outbound

This paper cites Ripple 2.0: High quality routability-driven placement via global router integration,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Ripple 2.0: High quality routability-driven placement via global router integration,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:55.951619Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e491e76a-8ff2-4c88-8b96-e696efac6543 · outbound

This paper cites Optimization of placement solutions for routability,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Optimization of placement solutions for routability,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:55.488249Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation ae8bcd75-0de1-407d-81df-11949cb2d9f6 · outbound

This paper cites Ntuplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Ntuplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:55.181974Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 67285d2b-dd54-4156-ac8f-a5fd0b12bc23 · outbound

This paper cites Fast and accurate routing demand estimation for efficient routability-driven placement,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Fast and accurate routing demand estimation for efficient routability-driven placement,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:54.847290Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 9470bb40-7abd-4527-b2e9-45a34e773139 · outbound

This paper cites Glare: Global and local wiring aware routability evaluation,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Glare: Global and local wiring aware routability evaluation,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:54.454382Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 38f3b937-f571-4d56-a87e-c5cca332e541 · outbound

This paper cites Ripple: A robust and effective routability-driven placer,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Ripple: A robust and effective routability-driven placer,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:54.101049Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation c5dc98ca-914c-4e87-ac5a-05d299a83137 · outbound

This paper cites Routability- driven global placer target on removing global and local congestion for vlsi designs,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Routability- driven global placer target on removing global and local congestion for vlsi designs,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:53.749584Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 05fd42cf-fcc7-44a5-8faa-67b4e950e613 · outbound

This paper cites Routenet: Routability prediction for mixed-size designs using convolutional neural network,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Routenet: Routability prediction for mixed-size designs using convolutional neural network,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:53.377017Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 5e8d71eb-12df-428e-b3ce-6ac7f061ab53 · outbound

This paper cites Mitigating distribution shift for congestion optimization in global placement,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Mitigating distribution shift for congestion optimization in global placement,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:53.024176Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation ce108ff1-35c2-423a-8996-561124c589a8 · outbound

This paper cites Versatile multi-stage graph neural network for circuit representation,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Versatile multi-stage graph neural network for circuit representation,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:52.673342Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 969d8c63-f9ba-4c80-aa00-04fa947fb9eb · outbound

This paper cites Congestionnet: Routing congestion prediction using deep graph neural networks,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Congestionnet: Routing congestion prediction using deep graph neural networks,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:52.348374Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 2f06d7d7-1d64-4ba4-824c-5ec6b3d98d5c · outbound

This paper cites Lhnn: lattice hypergraph neural network for vlsi congestion prediction,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Lhnn: lattice hypergraph neural network for vlsi congestion prediction,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:43.425134Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 561d0abf-2f08-4a5b-8c06-f4e048981020 · outbound

This paper cites Generalizable cross-graph embedding for gnn-based congestion prediction,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Generalizable cross-graph embedding for gnn-based congestion prediction,

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:43.568218Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation edddf0ce-a28d-49b9-8cfd-cb27c9bbf6b0 · outbound

This paper cites Lay-net: Grafting netlist knowledge on layout-based congestion prediction,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Lay-net: Grafting netlist knowledge on layout-based congestion prediction,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:52.057288Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation f5172705-8968-4c14-9bef-b02ae830e02d · outbound

This paper cites Pin accessibility and routing congestion aware DRC hotspot prediction using graph neural network and u-net,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Pin accessibility and routing congestion aware DRC hotspot prediction using graph neural network and u-net,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:51.783875Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 5102caaa-c69f-4166-836c-b7a87170b3b7 · outbound

This paper cites A timing engine inspired graph neural network model for pre-routing slack prediction,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code A timing engine inspired graph neural network model for pre-routing slack prediction,

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:43.943475Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d2374753-253e-448b-a45f-b3752e8f8b74 · outbound

This paper cites Tf-predictor: Transformer-based prerouting path delay prediction framework,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Tf-predictor: Transformer-based prerouting path delay prediction framework,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:51.456217Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 40d88bad-3c1e-4093-a89c-048752fe2102 · outbound

This paper cites Evaluating Large Language Models Trained on Code.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Evaluating Large Language Models Trained on Code

Reference 40

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:44.200813Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ea2d9f03-59de-4262-9dd0-7ee4ce7ddd92 · outbound

This paper cites CodeBERT: A pre-trained model for programming and natural languages,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code CodeBERT: A pre-trained model for programming and natural languages,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:51.086503Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 18a4aabb-1ff9-4e11-8b42-9197adede3bc · outbound

This paper cites Graphcode{bert}: Pre-training code representations with data flow,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Graphcode{bert}: Pre-training code representations with data flow,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:50.816697Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d15e69a7-9b48-4253-8334-26c30722dd62 · outbound

This paper cites Inferfix: End-to-end program repair with llms,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Inferfix: End-to-end program repair with llms,

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:44.679950Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cd11d782-d712-4988-84e9-8ed70f28e807 · outbound

This paper cites Enhancing static analysis for practical bug detection: An llm-integrated approach,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Enhancing static analysis for practical bug detection: An llm-integrated approach,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:50.527287Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 0d461749-b714-4e0a-acb5-bae527446eb8 · outbound

This paper cites LLM-Powered Test Case Generation for Detecting Bugs in Plausible Programs.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code LLM-Powered Test Case Generation for Detecting Bugs in Plausible Programs

Reference 45

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.021276Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3aecd6ac-9ad6-4ea0-a653-be4207954e27 · outbound

This paper cites Sanitizing large language models in bug detection with data-flow,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Sanitizing large language models in bug detection with data-flow,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:50.258469Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 1c3ad301-62a9-4c24-bff8-a50355552c6d · outbound

This paper cites Verigen: A large language model for verilog code generation,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Verigen: A large language model for verilog code generation,

Reference 47

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.332316Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8f07c259-ba52-4803-89c9-4c4623854bd6 · outbound

This paper cites Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,

Reference 48

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:49.954238Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation b89db61c-a286-4337-9599-cdc713bc6500 · outbound

This paper cites VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 49

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.594753Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 18690668-f321-491f-b41d-112a897f1451 · outbound

This paper cites Rtllm: An open-source benchmark for design rtl generation with large language model,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Rtllm: An open-source benchmark for design rtl generation with large language model,

Reference 50

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.714803Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 520549f3-3cdb-4526-b9ef-f95cbc7af926 · outbound

This paper cites CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Reference 51

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:45.891832Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0ebcd8fe-4626-43d9-af93-d80955b6b5c1 · outbound

This paper cites BetterV: Controlled verilog generation with discriminative guidance,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code BetterV: Controlled verilog generation with discriminative guidance,

Reference 52

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:49.620290Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8db082dd-76ef-4d61-a987-ff36c8bf4fee · outbound

This paper cites RTLRewriter: Methodologies for Large Models aided RTL Code Optimization.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

Reference 53

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:46.257689Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f0cfc682-a175-4141-8ba5-2ec547077db0 · outbound

This paper cites RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

Reference 54

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:46.420460Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9befa78a-8a1f-4089-97eb-aa0905c9e9c9 · outbound

This paper cites Lightgbm: A highly efficient gradient boosting decision tree,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Lightgbm: A highly efficient gradient boosting decision tree,

Reference 55

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:46.537219Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 74680d23-a360-4393-a67f-f3ee0a486955 · outbound

This paper cites When do neural nets outperform boosted trees on tabular data?.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code When do neural nets outperform boosted trees on tabular data?

Reference 56

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:49.316707Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d6b0e4c6-02ba-4bea-a6ad-81f3190c36b4 · outbound

This paper cites an unresolved cited work.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Unresolved cited work

Reference 57

Resolution: unresolved; raw_fallback, observed 2026-08-07T05:43:48.998845Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation decc694c-0748-4d53-b1fc-e1049b1cb1dc · outbound

This paper cites Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond

Reference 58

Resolution: verified exact; local_arxiv, observed 2026-08-07T05:43:47.418464Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3bea77e5-33b7-49d5-92c8-1a97e1ed270a · outbound

This paper cites Automated concatenation of embeddings for structured prediction,.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Automated concatenation of embeddings for structured prediction,

Reference 59

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T05:43:48.664969Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 0ee97ad5-331a-4129-a39e-8065775dce87 · outbound

This paper cites Beyond Decoder-only: Large Language Models Can be Good Encoders for Machine Translation.

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code Beyond Decoder-only: Large Language Models Can be Good Encoders for Machine Translation

Reference 2025

Resolution: unresolved; no resolver link, observed 2026-08-07T05:43:40.696475Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

Observation 60820d40-6652-4913-a2d9-8370a89a86e4 · inbound

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog cites this paper.

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

Reference 11

Resolution: verified exact; arxiv_id, observed 2026-05-10T11:45:21.410136Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.