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REVIEW 4 major objections 6 minor 71 references

ScalableHD: Scalable and High-Throughput Hyperdimensional Computing Inference on Multi-Core CPUs

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Hyperdimensional computing inference on multi-core CPUs can run 10x faster with a two-stage streaming pipeline

desk verdict A solid engineering paper on CPU HDC inference; the 10x throughput claim is plausible, but the 'near-proportional' scaling claim does not match the paper's own data. read the letter →

arxiv 2506.09282 v1 pith:U2JW2GOE submitted 2025-06-10 cs.DC cs.LG

Dhruv Parikh , Viktor Prasanna This is my paper
classification cs.DCcs.LG
keywords hyperdimensionalcomputingHDCinferencemulti-coreCPUtwo-stagepipelinememorytilingNUMA-awarebindingthroughputscalability
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Hyperdimensional computing (HDC) classifies data by mapping features into high-dimensional vectors and comparing them against learned class vectors, but efficient inference has mostly targeted GPUs and FPGAs. This paper argues that general-purpose multi-core CPUs can serve this workload at high throughput by restructuring inference into a two-stage pipeline that streams intermediate vectors between cores instead of materializing them in memory. The proposed method, ScalableHD, reports up to a 10x throughput improvement over the state-of-the-art CPU baseline [67] across eight datasets, with no change to the trained model or its accuracy. The paper further shows near-proportional throughput gains as the number of cores grows, which would make HDC a practical real-time inference option on commodity servers.

What carries the argument

The central mechanism is a two-stage pipelined execution model. Stage I (feature encoding) computes tiles of the encoded matrix $H = \mathrm{HardSign}(XB)$, where $B \in \mathbb{R}^{F \times D}$ is the learned base hypervector matrix. Stage II (similarity search and classification) multiplies those tiles by the transposed class matrix $M^\top$ and applies the argmax to produce labels. Instead of materializing the full $N \times D$ intermediate, the stages communicate through lock-free producer-consumer queues, so Stage II begins as soon as a tile of $H$ is ready. Memory tiling divides $X$, $B$, and $M^\top$ into cache-sized blocks, and NUMA-aware binding co-locates communicating workers on the same node, which together address the memory-bound data movement that dominates HDC inference on modern CPUs.

What would settle it

Benchmark a hand-optimized GEMM-based HDC inference implementation, for example using a tuned BLAS or oneDNN for the two matrix multiplications with the HardSign fused into the first multiplication, on the same two server platforms and eight datasets; if that baseline matches or exceeds ScalableHD's throughput on most configurations, the 10x advantage would reflect an unoptimized comparison baseline rather than the pipeline itself.

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Extended reading notes

Core claim

ScalableHD claims that the two matrix multiplications that constitute HDC inference—encoding a batch as $H = \mathrm{HardSign}(XB)$, then scoring classes as $S = HM^\top$ and taking the argmax—can be executed on multi-core CPUs with roughly an order of magnitude higher throughput than current CPU baselines. The key is to avoid storing the full $N \times D$ intermediate matrix $H$: Stage I workers compute column-block tiles of $H$ and stream them through lock-free queues to Stage II workers, which consume the tiles on the fly and accumulate partial similarity scores. Two execution variants are proposed, one that parallelizes Stage II along the vector dimensionality for small batches and one that parallelizes along the sample dimension for large batches. Memory tiling and NUMA-aware worker-to-core binding are added to keep the streaming pipeline cache-friendly. If the claims hold, the exact same trained model produces identical predictions while CPU inference throughput increases by up to 10x and scales near-linearly with core count.

Load-bearing premise

The speedup claim rests on the baseline library [67] being a representative, reasonably well-optimized CPU implementation of HDC inference, and on the tile-size and chunk-count configurations used for ScalableHD being representative of the method rather than tuned per dataset.

Editorial extensions

If this is right

  • The same trained HDC model can serve real-time workloads on commodity multi-core CPUs at up to 10x the throughput of the baseline [67], with identical classifications.
  • Near-proportional scaling with core count means adding cores directly increases samples-per-second throughput, without algorithmic changes.
  • Because the pipeline only reorganizes the arithmetic, it applies to any HDC method that uses nonlinear encoding, so recent accuracy improvements transfer unchanged.
  • The two variants cover both small-batch latency-sensitive inference and large-batch throughput-oriented inference, so one framework addresses both regimes.
  • If the results generalize, HDC becomes a more credible CPU-only alternative to neural networks for low-latency streaming classification.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the speedup comes from data movement, not arithmetic complexity, combining this pipeline with quantization or lower-precision hypervectors could yield further throughput gains, at some accuracy cost.
  • The same tiled streaming strategy is applicable to other inference workloads whose computation is two matrix multiplications separated by an elementwise activation, such as certain feedforward networks or embedding-based models.
  • A stricter evaluation would also sweep the baseline's hyperparameters and report a single fixed (n, R) configuration for ScalableHD rather than the maximum over four; without that control, the 10x figure likely overstates the advantage over a well-tuned GEMM baseline.
  • The all-to-all communication in the large-batch variant may become a contention point at extremely high thread counts, suggesting that dynamic load balancing or hierarchical streaming would be a natural next step.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper proposes ScalableHD, a two-stage pipelined implementation of hyperdimensional computing (HDC) inference on multi-core CPUs. Stage I computes the encoded hypervector matrix H = HardSign(XB) for an input batch X, base matrix B, and class matrix M; Stage II computes similarity scores S = HM^T and returns the argmax class. Two variants, ScalableHD-S and ScalableHD-L, target small and large batch sizes respectively, and the implementation uses lock-free queues, memory tiling, and NUMA-aware worker-to-core binding. The evaluation compares throughput (samples/s) against TorchHD on two server CPUs across eight datasets, reporting speedups up to 10x (with some datasets reaching 18x in the body text) while preserving task accuracy. The paper claims near-proportional scaling with increasing core count.

Significance. If the results hold, the paper addresses a genuine gap: efficient HDC inference on general-purpose multi-core CPUs, which prior work has largely neglected in favor of FPGAs, GPUs, and PIM/CIM. The matrix formulation is exact, so the accuracy-preservation claim is structurally guaranteed, and I see no circularity in the evaluation. The two-stage pipeline with producer-consumer streaming and memory tiling is a plausible engineering contribution, and the ablation study demonstrates that both optimizations matter. The main risks are the overstated scalability claim, an unfair baseline-comparison protocol, and inconsistent headline speedup numbers, all of which are fixable with revised claims and additional experiments.

major comments (4)
  1. [§IV-E, Fig. 8, abstract] The abstract says that increasing the number of cores yields 'near-proportional throughput improvements', and the conclusion repeats 'scaling near-linearly'. The data in Fig. 8 do not support this claim. For ideal proportional scaling, speedup from 2 to 32 cores would be 16x; the curves for MNIST, PAMAP2, and HEART on the AMD platform flatten between roughly 4x and 6x, implying parallel efficiency of 25-40%. The text in §IV-E itself retreats to the weaker phrase 'near log-linear scaling', which is not the same as 'near-proportional'. Because scalability is a headline contribution, this inconsistency is load-bearing. The authors should either correct the abstract and conclusion to say 'near log-linear' and discuss the memory-bandwidth limits causing the flattening, or provide additional evidence for proportional scaling at smaller core counts.
  2. [§IV-C, Fig. 7 caption] The evaluation protocol compares the maximum throughput of ScalableHD across four (n,R) hyperparameter combinations with a single TorchHD run at each (N,2T) pair. Selecting the best of four configurations for the proposed method while fixing the baseline to one configuration is not a like-for-like comparison. TorchHD's CPU kernels may themselves have tunable parameters (e.g., thread scheduling, internal blocking) that are left at defaults. The speedup results in Fig. 7 and Table III should be recomputed either with a pre-selected (n,R) configuration for ScalableHD or with equivalent tuning applied to TorchHD. At minimum, the paper should report the full range across (n,R) and justify that the best-of-four selection does not overstate the improvement.
  3. [Abstract, §IV-D, Table III] The abstract and conclusion state 'up to 10x speedup', but §IV-D and Table III report up to 18x speedup for TEX on the AMD platform (17.64x at N=32768). Conversely, Table III also shows speedups below 1x for small batches on some datasets (e.g., EMOTION ScalableHD-S at N=256, 0.59x). The paper gives at least three different headline numbers (10x, 18x, and the figures show other maxima), which is confusing and undermines the central claim. The authors need a single consistent statement of the maximum speedup, the exact configuration (dataset, platform, batch size, variant) at which it is achieved, and a clear qualification that small-batch/low-core regimes do not achieve speedups.
  4. [Table III, MNIST row] For MNIST on the AMD platform, Table III shows ScalableHD-L throughput of 24,776 samples/s at N=2048, roughly flat at N=8192 (24,747), and dropping to 20,540 at N=32768. This is a 17% decrease at the largest batch size. The ScalableHD-L variant is described as designed for 'high-throughput processing of large batches', yet the largest batch size gives the lowest throughput. This non-monotonic behavior should be explained. If it is caused by DRAM bandwidth saturation (with D=10000, B and M are hundreds of MB), the paper should say so in §IV-E and qualify the 'high-throughput' claim accordingly.
minor comments (6)
  1. [§II-A, Eq. (2)] The bundling symbol is rendered inconsistently: the text defines the operation with a symbol that appears as 'L' in the extraction, but Eq. (2) and later text use '⊕'. Please unify the notation.
  2. [§IV-C, Eq. (10)] The throughput formula is ambiguous as written: 'throughput (samples/sec)= 1000 N·latency (ms)' should be '1000 * N / latency(ms)'. Please clarify the formula with the division.
  3. [Algorithm 4, line 10] The indexing in 'S^{(t')}[i][k] += H^{(t',j)}[i][j] J[j][k]' is inconsistent with the block notation; 'i' is a row block and 'j' is a column block of H, so the element should be indexed with a column index within block (j), not with 'j' itself. Please correct the notation.
  4. [§IV-C, batch-size ranges] The batch-size specification 'log2N ∈ {5,6,...,11} for S and {10,...,15} for L' is confusing. State the actual N ranges (32-2048 for S, 1024-32768 for L) and note that N=1024 and 2048 are shared between the two variants.
  5. [Fig. 8] To visually support a 'near-proportional' scaling claim, a log-log plot would be more appropriate, since proportional scaling (speedup ∝ core count) appears as a straight line with slope 1. The current semi-log plot makes it hard to distinguish near-linear from near-log-linear trends.
  6. [General] The paper would benefit from a statement about code availability. Providing a public repository would improve reproducibility of the performance numbers and the exact matrix-based implementation.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: ScalableHD is an empirical systems-optimization paper benchmarked against an external baseline, with no input-output derivation that reduces to its own assumptions.

full rationale

The paper makes no first-principles derivation whose output is equivalent to its input. Its central claims are measured throughput speedup over TorchHD and multi-core scalability. Throughput is defined operationally in Eq. (10) from end-to-end latency, and speedup in Eq. (11) is a ratio of independently measured throughputs against TorchHD, an external open-source library (ref. [67]). The HDC inference computation (Eqs. 4-9) is standard and unchanged from the trained model, so accuracy preservation follows from the algorithm being unmodified rather than from any circular fit. The hyperparameters (tile sizes n=f=d=k, chunk count R) are heuristic and are not defined in terms of the measured speedup or the baseline. The ablation study reports actual relative gains from enabling optimizations, which is an engineering measurement, not a tautology. The skeptical observation that Fig. 8 shows sub-linear scaling for several datasets is a concern about the strength of the empirical scalability claim, but it is a correctness/evidence issue, not a circularity issue. No self-citation is load-bearing, no uniqueness theorem is imported, and no prediction is constructed from its own definition. Therefore the paper is self-contained as an empirical benchmark and receives score 0.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The performance claims rest on hand-tuned tile sizes and chunk counts, a hardware-behavior assumption, and a baseline fairness assumption. The paper introduces no new mathematical entities, particles, or data structures beyond standard HDC vectors and matrices.

free parameters (2)
  • tile size n=f=d=k = {16, 32}
    Chosen heuristically to fit first-level cache; the reported throughput at each workload is the maximum over these values, so the headline speedup depends on this hand-tuned selection.
  • tiles per round R = {8, 16}
    Selected to enable last-level-cache reuse; as with tile size, the evaluation takes the maximum throughput across these values when reporting speedups.
assumptions (3)
  • domain assumption Bipolar HDC algebra with inner-product similarity is the workload to accelerate
    Adopted from TrainableHD and nonlinear encoding [4], [22]; the systems claim assumes this exact computation is representative of HDC inference.
  • domain assumption CPU performance is memory-bound and improved by cache reuse and NUMA locality
    The two-stage tiling design assumes this hardware model; no quantitative performance model is derived or validated.
  • ad hoc to paper TorchHD with the same batch size and core count is a fair state-of-the-art CPU baseline
    The entire speedup comparison rests on this assumption; if TorchHD's CPU kernels are weak, the speedup is inflated. Introduced in Section IV-C.

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Cite this review

Pith. "Pith review of ScalableHD: Scalable and High-Throughput Hyperdimensional Computing Inference on Multi-Core CPUs." pith.science (2026). https://pith.science/paper/U2JW2GOE

@misc{pith2026250609282,
  author       = {Pith},
  title        = {Pith review of: ScalableHD: Scalable and High-Throughput Hyperdimensional Computing Inference on Multi-Core CPUs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U2JW2GOE}},
  note         = {Machine review of arXiv:2506.09282}
}
read the original abstract

Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm that represents and manipulates information using high-dimensional vectors, called hypervectors (HV). Traditional HDC methods, while robust to noise and inherently parallel, rely on single-pass, non-parametric training and often suffer from low accuracy. To address this, recent approaches adopt iterative training of base and class HVs, typically accelerated on GPUs. Inference, however, remains lightweight and well-suited for real-time execution. Yet, efficient HDC inference has been studied almost exclusively on specialized hardware such as FPGAs and GPUs, with limited attention to general-purpose multi-core CPUs. To address this gap, we propose ScalableHD for scalable and high-throughput HDC inference on multi-core CPUs. ScalableHD employs a two-stage pipelined execution model, where each stage is parallelized across cores and processes chunks of base and class HVs. Intermediate results are streamed between stages using a producer-consumer mechanism, enabling on-the-fly consumption and improving cache locality. To maximize performance, ScalableHD integrates memory tiling and NUMA-aware worker-to-core binding. Further, it features two execution variants tailored for small and large batch sizes, each designed to exploit compute parallelism based on workload characteristics while mitigating the memory-bound compute pattern that limits HDC inference performance on modern multi-core CPUs. ScalableHD achieves up to 10x speedup in throughput (samples per second) over state-of-the-art baselines such as TorchHD, across a diverse set of tasks ranging from human activity recognition to image classification, while preserving task accuracy. Furthermore, ScalableHD exhibits robust scalability: increasing the number of cores yields near-proportional throughput improvements.

Figures

Figures reproduced from arXiv: 2506.09282 by the authors.

Figure 1
Figure 1. Overview of the proposed ScalableHD method. FE [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Stage I. Each worker computes a subset of output [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 4
Figure 4. Stage II of ScalableHD-L. All Stage I workers ( [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figures from the paper (6 more)
Figure 3
Figure 3. Figure 3: Stage II of ScalableHD-S. Worker t0 in Stage I computes column blocks 0 and 4 of H and streams them to its sibling worker t ′ 0 in Stage II. Worker t ′ 0 computes a partial of the full output matrix S (shown as S0) by multiplying each column block with the correspondin…
Figure 5
Figure 5. Figure 5: Memory tiling of X, B, and J. Green (red) arrows indicate row-major (column-major) layout at both the inter￾block and intra-block (elements within a block) level. (left matrix) and B (right matrix), enabling efficient streaming memory access and improved cache utilizat…
Figure 6
Figure 6. Figure 6: NUMA-aware worker-to-core binding. Example shown [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: Speedup of ScalableHD over TorchHD for 8 datasets across AMD ( [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 8
Figure 8. Figure 8: Scalability of ScalableHD across number of cores for 8 datasets on AMD ( [PITH_FULL_IMAGE:figures/full_fig_p012_8.png]
Figure 9
Figure 9. Figure 9: Ablation study analyzing the impact of optimizations [PITH_FULL_IMAGE:figures/full_fig_p013_9.png]

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.