EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques | Paper Citation Record

Observation f77fd37e-41a4-4405-a221-f1c9c3a047bd · outbound

This paper cites Memory Scaling: A Systems Architecture Perspective,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Memory Scaling: A Systems Architecture Perspective,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.368032Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6a07da18-09cb-45f3-bcf2-bfa0edfd8043 · outbound

This paper cites A Modern Primer On Processing In Memory,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Modern Primer On Processing In Memory,

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.506238Z

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Observation 8b8f3217-9bf8-4568-9cda-88ce145d36a4 · outbound

This paper cites Processing-in- memory: A Workload-driven Perspective,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Processing-in- memory: A Workload-driven Perspective,

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.659172Z

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Unavailable: canonical work link unavailable.

Observation a1fb14c7-e200-46a0-9a13-758ee5f2a875 · outbound

This paper cites A Modern Primer on Processing in Memory.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Modern Primer on Processing in Memory

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.761136Z

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Observation ee642977-bb26-48f9-895c-c326e67f7784 · outbound

This paper cites Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.851558Z

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Observation 813c0876-85b8-467f-9b98-4a39ed388d19 · outbound

This paper cites Reducing DRAM Latency Via Charge-level-aware Look-ahead Partial Restoration,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Reducing DRAM Latency Via Charge-level-aware Look-ahead Partial Restoration,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.918054Z

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Observation 64ea8b64-08a3-4781-8fc2-376eceaea4ef · outbound

This paper cites HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the- shelf DRAM Chips,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the- shelf DRAM Chips,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:32.982540Z

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Unavailable: canonical work link unavailable.

Observation e556bec5-0612-4ad0-81aa-d6aaa3e00771 · outbound

This paper cites CLR-DRAM: A Low-cost DRAM Architecture Enabling Dynamic Capacity-latency Trade-off,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques CLR-DRAM: A Low-cost DRAM Architecture Enabling Dynamic Capacity-latency Trade-off,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.051370Z

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Unavailable: canonical work link unavailable.

Observation 6f336d29-7602-4896-b9ef-0dde3efdc184 · outbound

This paper cites VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.150863Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9684898b-1d96-4974-8057-3f46c768d0ab · outbound

This paper cites ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.256839Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0fb3beb3-1d57-4d70-8ab3-ebf79e25a91b · outbound

This paper cites Tiered-latency DRAM: A Low Latency and Low Cost DRAM Architecture,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Tiered-latency DRAM: A Low Latency and Low Cost DRAM Architecture,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.317142Z

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Unavailable: canonical work link unavailable.

Observation a857b70c-45d9-489f-9928-67fef1c7f503 · outbound

This paper cites Adaptive-latency DRAM: Optimizing DRAM Timing for the Common-case,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Adaptive-latency DRAM: Optimizing DRAM Timing for the Common-case,

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.397755Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 70270aa8-8e9a-4ef2-8a1d-eefdcdd979d1 · outbound

This paper cites Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.563289Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c11d7af7-b994-41df-9761-100eb66892d3 · outbound

This paper cites Understanding and Improving the Latency of DRAM-based Memory Systems,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Understanding and Improving the Latency of DRAM-based Memory Systems,

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.718438Z

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Unavailable: canonical work link unavailable.

Observation 13574093-0c5c-4d21-9d86-8ec68f67b0b2 · outbound

This paper cites Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM,

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:33.860685Z

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Observation 5e75d2ef-49b4-4c48-bf1c-c511f2500076 · outbound

This paper cites Low-cost Inter-linked Subarrays (LISA): Enabling Fast Inter-subarray Data Movement in DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Low-cost Inter-linked Subarrays (LISA): Enabling Fast Inter-subarray Data Movement in DRAM,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.018915Z

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Unavailable: canonical work link unavailable.

Observation d960e031-5258-4537-9fde-d3bb7a3d886f · outbound

This paper cites Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.178159Z

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Observation 4564a48c-0f6a-4931-84f3-b9456bdc1c09 · outbound

This paper cites Simultaneous Many- row Activation in Off-the-shelf DRAM Chips: Experimental Characterization and Analysis,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Simultaneous Many- row Activation in Off-the-shelf DRAM Chips: Experimental Characterization and Analysis,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.306290Z

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Observation 97f0e3e8-691d-4121-9a38-ee094574e414 · outbound

This paper cites Functionally-complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Functionally-complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis,

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.464377Z

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Observation 133d941c-ab7b-4d80-9356-e78f82dc641c · outbound

This paper cites QUAC-TRNG: High-throughput True Random Number 13 Generation using Quadruple Row Activation in Commodity DRAM Chips,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques QUAC-TRNG: High-throughput True Random Number 13 Generation using Quadruple Row Activation in Commodity DRAM Chips,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.592741Z

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Observation 547f1721-0762-4574-aff7-34b5d9fdf01c · outbound

This paper cites CROW: A Low-cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques CROW: A Low-cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability,

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.711376Z

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Observation 12a23bff-4398-4afd-8e9f-547318b1645c · outbound

This paper cites Using Run-Time Reverse-Engineering to Optimize DRAM Refresh,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Using Run-Time Reverse-Engineering to Optimize DRAM Refresh,

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.800165Z

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Observation fa618e3f-687c-4c8f-b816-bcfa496d7080 · outbound

This paper cites EDEN: Enabling Energy-efficient, High-performance Deep Neural Network Inference Using Approximate DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques EDEN: Enabling Energy-efficient, High-performance Deep Neural Network Inference Using Approximate DRAM,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:34.914406Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ed9560c2-69f1-439a-8ed5-0a90f367bb39 · outbound

This paper cites Orosa, S.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Orosa, S

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:54.162290Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d470f1be-c887-4265-af84-8aaa693f5d82 · outbound

This paper cites Exploiting Expendable Process-margins In Drams For Run-time Performance Optimization,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Exploiting Expendable Process-margins In Drams For Run-time Performance Optimization,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:54.061432Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1e016dac-86d4-4d80-bbdd-66447827b57d · outbound

This paper cites CDAR-DRAM: Enabling Run- time DRAM Performance And Energy Optimization Via In-situ Charge Detection And Adaptive Data Restoration,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques CDAR-DRAM: Enabling Run- time DRAM Performance And Energy Optimization Via In-situ Charge Detection And Adaptive Data Restoration,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.937004Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ecbaebe4-84e3-4546-81ca-200d3ab6954a · outbound

This paper cites Restore Truncation For Performance Improvement In Future DRAM Systems,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Restore Truncation For Performance Improvement In Future DRAM Systems,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.810139Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f08685db-2687-4d87-a111-a9c64dd18fb9 · outbound

This paper cites NUAT: A Non-uniform Access Time Memory Controller,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques NUAT: A Non-uniform Access Time Memory Controller,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.695652Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 2245e424-3278-49da-afc8-94507831acaf · outbound

This paper cites Dram-latency Optimization Inspired By Relationship Between Row-access Time And Refresh Timing,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Dram-latency Optimization Inspired By Relationship Between Row-access Time And Refresh Timing,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.570632Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 3d7fbc18-e004-45c3-8a98-a7f1e75951e0 · outbound

This paper cites Prelatpuf: Exploiting DRAM Latency Variations For Generating Robust Device Signatures,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Prelatpuf: Exploiting DRAM Latency Variations For Generating Robust Device Signatures,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.445860Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cc4f5983-9a1a-40cd-9a15-94dd59577986 · outbound

This paper cites D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.327253Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 656bdb45-e988-4840-8f9f-2a493103b09a · outbound

This paper cites FracDRAM: Fractional Values in Off- the-shelf DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques FracDRAM: Fractional Values in Off- the-shelf DRAM,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.165189Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fb716227-a8cf-4b6d-96eb-7073539ec495 · outbound

This paper cites CODIC: A Low-cost Substrate for Enabling Custom In-DRAM Functionalities and Optimiza- tions,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques CODIC: A Low-cost Substrate for Enabling Custom In-DRAM Functionalities and Optimiza- tions,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:53.032282Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 7978f80e-0ef5-4be4-bbde-a51cc892ddbc · outbound

This paper cites DR-STRaNGe: End-to-end System Design For Dram-based True Random Number Generators,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques DR-STRaNGe: End-to-end System Design For Dram-based True Random Number Generators,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.872417Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 6aeaefb7-4f59-4fd7-9a0d-bec07a7a6242 · outbound

This paper cites ComputeDRAM: In-memory Compute using Off-the-shelf DRAMs,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques ComputeDRAM: In-memory Compute using Off-the-shelf DRAMs,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.745378Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation bd0a8eeb-82f0-42bf-82a6-1d7e3d5d2db0 · outbound

This paper cites The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting The Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting The Latency-Reliability Tradeoff in Modern Commodity DRAM Devices,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.647310Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 726d630f-7acf-4e01-a238-4515b4036ffe · outbound

This paper cites an unresolved cited work.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Unresolved cited work

Reference 37

Resolution: unresolved; raw_fallback, observed 2026-08-07T04:34:52.508389Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 757e8136-a5d8-4307-859a-17c036b3d745 · outbound

This paper cites an unresolved cited work.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Unresolved cited work

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:36.162881Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a951c459-56a0-4bc6-a1a5-a20fa92a911b · outbound

This paper cites RowClone: Fast and Energy-efficient In-DRAM Bulk Data Copy and Initialization,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques RowClone: Fast and Energy-efficient In-DRAM Bulk Data Copy and Initialization,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.372449Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ed58af14-f47b-44d8-bd33-5b26cc0e63a6 · outbound

This paper cites PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.242229Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 439f6199-43e6-42b6-8f86-eeeba8bf8af6 · outbound

This paper cites DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:52.115160Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 2bcc0ae1-80ce-45c3-b5d8-50492a4f7395 · outbound

This paper cites an unresolved cited work.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Unresolved cited work

Reference 42

Resolution: unresolved; raw_fallback, observed 2026-08-07T04:34:51.959353Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5aa6f366-a65d-4c79-a669-dfdf5ca96f6e · outbound

This paper cites an unresolved cited work.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Unresolved cited work

Reference 43

Resolution: unresolved; raw_fallback, observed 2026-08-07T04:34:51.830397Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 33865e2c-3e07-4219-b318-1aec1209ec6c · outbound

This paper cites The gem5 Simulator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The gem5 Simulator,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:51.706672Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cbdc2bc7-52be-4456-b4f1-0d5fa57abc2f · outbound

This paper cites Ramulator: A Fast And Extensible DRAM Simulator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Ramulator: A Fast And Extensible DRAM Simulator,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:51.538357Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 41a29eaa-d73c-4a15-b7e1-7058ad160fe5 · outbound

This paper cites Sim2PIM: A Complete Simulation Framework for Processing-in-memory,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Sim2PIM: A Complete Simulation Framework for Processing-in-memory,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:51.416768Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e111a81a-170c-475f-9844-5c791832176b · outbound

This paper cites Gem5-GPU: A Hetero- geneous CPU-GPU Simulator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Gem5-GPU: A Hetero- geneous CPU-GPU Simulator,

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:51.237068Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 7abe1b15-4b6d-49e1-aa33-b9a8c216d102 · outbound

This paper cites Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator,

Reference 48

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:51.065520Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c0d39f39-1a04-43df-9b4f-dc7e58c26165 · outbound

This paper cites Flipping Bits in Memory without Accessing Them: An Experimental Study of DRAM Disturbance Errors,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Flipping Bits in Memory without Accessing Them: An Experimental Study of DRAM Disturbance Errors,

Reference 49

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.895208Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 18d4501f-9c4e-415b-9d1f-861212bba26c · outbound

This paper cites A Deeper Look Into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Deeper Look Into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,

Reference 50

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.748145Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fda5e01b-daf6-4746-afa7-cc7c91c71461 · outbound

This paper cites Spatial Variation-aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Spatial Variation-aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,

Reference 51

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.620029Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 9b6a3c3a-bf22-4684-8967-5359792368ed · outbound

This paper cites Understanding Rowhammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Understanding Rowhammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,

Reference 52

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.490993Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5138285f-8514-4ebe-b5d4-941fc4680584 · outbound

This paper cites Strober: Fast and Accurate Sample-based Energy Simulation for Arbitrary RTL,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Strober: Fast and Accurate Sample-based Energy Simulation for Arbitrary RTL,

Reference 53

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.358080Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a2dcad46-b695-4444-b32e-7cc4aef872ef · outbound

This paper cites Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs,

Reference 54

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.208099Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e84f7633-8abe-4a6d-bc40-b5952e19175e · outbound

This paper cites SoftMC: A Flexible and Practical Open-source Infrastruc- ture for Enabling Experimental DRAM Studies,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques SoftMC: A Flexible and Practical Open-source Infrastruc- ture for Enabling Experimental DRAM Studies,

Reference 55

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:50.098052Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 96b8cd14-4813-46f3-a728-98cc231728ae · outbound

This paper cites FASED: FPGA-accelerated Simulation and Evaluation of DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques FASED: FPGA-accelerated Simulation and Evaluation of DRAM,

Reference 56

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.912104Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ce0e54bf-ae50-432e-9bdb-74fee1b2b8a2 · outbound

This paper cites FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud,

Reference 57

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.739081Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 943c70c0-460a-42a4-b907-ca07212bcc2b · outbound

This paper cites PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform,

Reference 58

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.572712Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5464bf37-3b33-4cec-bcb7-2cbff928ef74 · outbound

This paper cites FreezeTime: Towards System Emulation through Architectural Virtualization,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques FreezeTime: Towards System Emulation through Architectural Virtualization,

Reference 59

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.401324Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1de2a148-ff40-4f19-8e69-5bcc177e3ef3 · outbound

This paper cites The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,

Reference 60

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.261724Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 94429f46-6a56-4285-ae4d-17b55beb8701 · outbound

This paper cites A Reconfigurable Real-time SDRAM Controller for Mixed Time-criticality Systems,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Reconfigurable Real-time SDRAM Controller for Mixed Time-criticality Systems,

Reference 61

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:49.080626Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation cde7bae1-e21a-47d9-b139-414b0839b4c8 · outbound

This paper cites PARDIS: A Programmable Memory Controller For The DDRx Interfacing Standards,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques PARDIS: A Programmable Memory Controller For The DDRx Interfacing Standards,

Reference 62

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:48.908151Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 44ca3716-3715-40c8-8546-2648a87f640c · outbound

This paper cites Polybench: The Polyhedral Benchmark Suite,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Polybench: The Polyhedral Benchmark Suite,

Reference 63

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:48.660635Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation b2dc52bb-064d-4009-9d7a-ee7473bbe012 · outbound

This paper cites NVIDIA Jetson Nano,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques NVIDIA Jetson Nano,

Reference 64

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:48.465444Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f8d32a9a-82cb-4147-84bb-8ff8dde33eff · outbound

This paper cites Impulse: Building a Smarter Memory Controller,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Impulse: Building a Smarter Memory Controller,

Reference 65

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:48.267297Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0f79af63-3cae-42c0-aad3-ec54e84e70ad · outbound

This paper cites Improving DRAM Performance by Parallelizing Refreshes with Accesses,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Improving DRAM Performance by Parallelizing Refreshes with Accesses,

Reference 66

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:48.085446Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 11cd8e2f-fc7e-424e-adb6-974182055df5 · outbound

This paper cites Understanding Reduced-voltage Operation in Modern DRAM De- vices: Experimental Characterization, Analysis, and Mechanisms,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Understanding Reduced-voltage Operation in Modern DRAM De- vices: Experimental Characterization, Analysis, and Mechanisms,

Reference 67

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.896385Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c7608e3e-5cba-4904-a85c-541978b1a2a5 · outbound

This paper cites TRRespass: Exploiting The Many Sides of Target Row Refresh,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques TRRespass: Exploiting The Many Sides of Target Row Refresh,

Reference 68

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.724566Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 3f575551-b462-4dd8-9adf-397c994ffba8 · outbound

This paper cites What Your DRAM Power Models Are Not Telling You: Lessons From A Detailed Experimental Study,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques What Your DRAM Power Models Are Not Telling You: Lessons From A Detailed Experimental Study,

Reference 69

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.550977Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d4a9443c-480d-45d6-a9c9-1b0e20adc37a · outbound

This paper cites Self-optimizing Memory Con- trollers: A Reinforcement Learning Approach,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Self-optimizing Memory Con- trollers: A Reinforcement Learning Approach,

Reference 70

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.378855Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 2af74874-417b-4d35-aa5f-047f8e4ab738 · outbound

This paper cites ABACuS: All-bank Activation Counters for Scalable and Low Overhead Rowhammer Mitigation,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques ABACuS: All-bank Activation Counters for Scalable and Low Overhead Rowhammer Mitigation,

Reference 71

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.219014Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 78d79964-8767-47e7-85ce-438705b7e5e5 · outbound

This paper cites BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads,

Reference 72

Resolution: unresolved; no resolver link, observed 2026-08-07T04:34:40.231842Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dd35f2c5-8ce1-4f45-bb8e-668d434bd183 · outbound

This paper cites A Case for Exploiting Subarray-level Parallelism (SALP) in DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Case for Exploiting Subarray-level Parallelism (SALP) in DRAM,

Reference 73

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:47.029853Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c755ce2b-0bb4-40e3-b331-7cc6ed1d30a8 · outbound

This paper cites Controller for A Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests And Commands to be Issued Out Of Order,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Controller for A Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests And Commands to be Issued Out Of Order,

Reference 74

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.866261Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f1f934cd-e788-4705-933e-c8b9fad1ccf0 · outbound

This paper cites Memory Access Scheduling,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Memory Access Scheduling,

Reference 75

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.703624Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation a47d71bc-293f-497d-83d1-3fec72ef8d8b · outbound

This paper cites Parallelism-aware Batch Scheduling: Enhancing Both Performance And Fairness Of Shared DRAM Systems,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Parallelism-aware Batch Scheduling: Enhancing Both Performance And Fairness Of Shared DRAM Systems,

Reference 76

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.573589Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 39a79c17-1423-4c3f-9bcc-cfe55a87664d · outbound

This paper cites Stall-time Fair Memory Access Scheduling For Chip Multiprocessors,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Stall-time Fair Memory Access Scheduling For Chip Multiprocessors,

Reference 77

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.432449Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 73ce0f8d-071d-4e01-a096-8a1ce1c12f74 · outbound

This paper cites The Blacklisting Memory Scheduler: Achieving High Performance And Fairness At Low Cost,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The Blacklisting Memory Scheduler: Achieving High Performance And Fairness At Low Cost,

Reference 78

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.301049Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation d9ec632a-78f3-48b3-8daf-7139254edc91 · outbound

This paper cites BLISS: Balancing Performance, Fairness And Complexity In Memory Access Scheduling,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques BLISS: Balancing Performance, Fairness And Complexity In Memory Access Scheduling,

Reference 79

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.181928Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 3da56824-abb4-4bf5-a971-4f0ec849f42c · outbound

This paper cites OpenHW Group – Website,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques OpenHW Group – Website,

Reference 80

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:46.067980Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0cf5d2a3-0715-4228-8056-4d2323caefdc · outbound

This paper cites The Rocket Chip Generator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The Rocket Chip Generator,

Reference 81

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.906666Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 04e98bbb-2f73-4ee3-b3e6-4b63128cc127 · outbound

This paper cites IBM z15: A 12-Core 5.2GHz Microprocessor,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques IBM z15: A 12-Core 5.2GHz Microprocessor,

Reference 82

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.792911Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation eb34b287-bc94-4d47-b179-ee94466fafa2 · outbound

This paper cites IBM Telum: a 16-Core 5+ GHz DCM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques IBM Telum: a 16-Core 5+ GHz DCM,

Reference 83

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.696483Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fa2749f8-c608-4313-99b6-f68240679e1c · outbound

This paper cites DRAM Bender — Github Repository,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques DRAM Bender — Github Repository,

Reference 84

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.567587Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 10426beb-f06e-4599-9d82-78478aaa5434 · outbound

This paper cites Chisel: Constructing Hardware in a Scala Embedded Language,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Chisel: Constructing Hardware in a Scala Embedded Language,

Reference 85

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.468658Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 49c177a7-e567-4e31-ba47-05a6e7bd7231 · outbound

This paper cites A Highly Productive Implementation of an Out-of-order Processor Gen- erator,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques A Highly Productive Implementation of an Out-of-order Processor Gen- erator,

Reference 86

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.346335Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 9ccccc9f-fe64-4658-8635-ad962b6b942a · outbound

This paper cites LMbench: Portable Tools for Performance Analysis.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques LMbench: Portable Tools for Performance Analysis

Reference 87

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:45.141212Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation f85a1673-3e9d-4907-bbe7-a3acc7b470bd · outbound

This paper cites Xilinx VCU 108 FPGA Board,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Xilinx VCU 108 FPGA Board,

Reference 88

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.987645Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ace84d75-9777-4099-8abb-c235f9a7f79e · outbound

This paper cites Ramulator 2.0,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Ramulator 2.0,

Reference 89

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.854574Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation edc1934b-d77d-4ada-9ca2-cb1835d7f592 · outbound

This paper cites Design-induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Design-induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,

Reference 90

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.708138Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 572db324-99a0-4e63-a28d-10ec0640e839 · outbound

This paper cites DDR4 SDRAM EDY4016A - 256Mb x 16,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques DDR4 SDRAM EDY4016A - 256Mb x 16,

Reference 91

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.579275Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1fa58864-3d88-49ae-b797-546937ab5c96 · outbound

This paper cites Space/time Trade-offs In Hash Coding With Allowable Errors,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Space/time Trade-offs In Hash Coding With Allowable Errors,

Reference 92

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.414771Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 1e8ea48d-bbec-4dc4-8411-63fb0ef1c98a · outbound

This paper cites RAIDR: Retention-aware Intelligent DRAM Refresh,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques RAIDR: Retention-aware Intelligent DRAM Refresh,

Reference 93

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.339474Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 209ad862-08d9-4b52-9881-c35cdb76dcc5 · outbound

This paper cites MEG: A RISCV-based System Emu- lation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques MEG: A RISCV-based System Emu- lation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory,

Reference 94

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.230657Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 5d5aa6e9-c440-4d83-bde3-4be3dccfcaf6 · outbound

This paper cites Fast Bulk Bitwise AND And OR In DRAM,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Fast Bulk Bitwise AND And OR In DRAM,

Reference 95

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.113797Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation e82c35eb-7853-4693-8721-9662b0b6d938 · outbound

This paper cites Ambit: In-memory Accelerator For Bulk Bitwise Operations Using Commodity DRAM Technology,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Ambit: In-memory Accelerator For Bulk Bitwise Operations Using Commodity DRAM Technology,

Reference 96

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:44.034203Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fd857ab8-9772-41fa-b31d-7df0062d18a5 · outbound

This paper cites Softmc — Github Repository,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Softmc — Github Repository,

Reference 97

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:43.936099Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 0ddcc223-81ec-4df7-ac3b-03fe1f072bd0 · outbound

This paper cites The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions By Exploiting The Latency–reliability Tradeoff In Modern DRAM Devices,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions By Exploiting The Latency–reliability Tradeoff In Modern DRAM Devices,

Reference 98

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:43.767212Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 8aa4dc71-7e19-4a9e-a83f-ad10314aa27f · outbound

This paper cites Exploiting DRAM Latency Variations for Generating True Random Numbers,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques Exploiting DRAM Latency Variations for Generating True Random Numbers,

Reference 99

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:43.640863Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 131fcc7a-b2b3-43d8-be14-cde71d563c5d · outbound

This paper cites AVATAR: A Variable- retention-time (VRT) Aware Refresh for DRAM Systems,.

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques AVATAR: A Variable- retention-time (VRT) Aware Refresh for DRAM Systems,

Reference 100

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T04:34:43.471868Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Coverage vector

Reference resolution

Outbound references

Pith citing papers