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REVIEW 3 major objections 5 minor 32 references

X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A photonic SRAM bitcell stores one bit and computes the XOR of that bit with an incoming optical bit at 10 GHz, with wavelength multiplexing enabling n-bit XOR in a single shot.

desk verdict A genuinely new photonic in-memory XOR bitcell, but the headline 10/20 GHz and 13.2 fJ figures are extrapolated from isolated pulses and omit thermal tuning, so it is a promising design study, not a demonstrated performance result. read the letter →

arxiv 2506.22707 v1 pith:SOHTZARS submitted 2025-06-28 eess.SY cs.SY

Md Abdullah-Al Kaiser , Sugeet Sunder , Ajey P. Jacob , Akhilesh R. Jaiswal This is my paper · ORCID
classification eess.SYcs.SY
keywords photonicSRAMin-memorycomputingXORmicroringresonatorwavelength-divisionmultiplexingopticalelectro-opticlatch45SPCLO
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes a photonic static random access memory bitcell that both stores a binary value and performs an in-situ Boolean XOR between the stored bit and an incoming optical bit. The bitcell uses cross-coupled microring resonators and differential photodiodes to form an electro-optic latch, with two additional rings acting as compute gates whose thru-port light forms the XOR output. The authors claim at least 10 GHz read, write, and compute operation, and that wavelength-division multiplexing lets an array of these cells produce n XOR results in one shot. Simulation on GlobalFoundries' 45SPCLO node gives 13.2 fJ per XOR bit. If correct, this would make the XOR operation—ubiquitous in encryption, search, and binary neural networks—available inside memory at optical speed without moving data out.

What carries the argument

The core mechanism is a cross-coupled pair of microring resonators (M1, M2) and differential photodiodes (P1–P4) forming a bistable electro-optic latch, taken from the authors' prior pSRAM bitcell [30], plus two compute rings (M3, M4) and an MMI coupler that produce the XOR output. The latch state is set by which ring is in resonance; the compute rings are driven by the complementary storage nodes so that the combination of stored bit and input bits selects whether light reaches the output. The named identity is the X-pSRAM bitcell; the single-shot n-bit XOR comes from wavelength-division multiplexing, where each row's compute rings are tuned to a distinct resonance wavelength so that many wavelengths can be processed in parallel and read out separately at the combined Z node.

What would settle it

Fabricate the X-pSRAM cell in the 45SPCLO process with the stated ring radii, gaps, and wavelengths, then apply a 50 ps write pulse and a 100 ps compute pulse while monitoring the Y/YB node voltages and Z-port optical power over many cycles; if the latch fails to flip within the write pulse or the Z extinction ratio between equal and different inputs drops below the detection threshold, the claimed 10 GHz operation is falsified. A direct material check is to measure the photodiode responsivity and dark current at 1310.52 nm to confirm the 10 µW bias actually yields enough differential current to hold the latch against leakage and thermal drift.

Watch

Extended reading notes

Core claim

The central claim is that a single X-pSRAM bitcell stores one bit in a cross-coupled electro-optic latch and outputs at node Z the XOR of the stored bit Y with an input bit X: Z is dark when X=Y and bright when X≠Y. The computation happens in the optical domain: the input bit is carried as light on waveguides X and XB, and the read rings M3/M4 are driven by the complementary storage nodes; their thru ports combine through an MMI coupler so that equal values redirect the light into absorbers and differing values pass it to Z. The same cell also supports write (a 50 ps differential optical pulse flips the latch) and read (a pulse on XB produces active-high output at Z). The paper reports simulated operation at 10 GHz compute and up to 20 GHz write, with an 8-bit WDM demonstration where eight rows tuned to eight wavelengths compute an 8-bit XOR in one shot.

Load-bearing premise

The load-bearing premise is that the GF45SPCLO simulation models faithfully capture the transient behavior of the cross-coupled latch and differential photodiodes at 10 GHz; if the photodiode currents, ring coupling, or driver delays are optimistic, the 50 ps write pulse and 100 ps compute pulse will not flip or hold the latch, and the 20 GHz write / 10 GHz compute claims collapse.

Editorial extensions

If this is right

  • An array can perform a bitwise XOR between a stored word and an incoming word in a single optical pass, with each bit's result carried on its own wavelength.
  • Because the compute path is optical and the latch is electro-optic, XOR latency is set by the optical pulse width (100 ps) rather than by electrical word-line switching.
  • XNOR is available with no extra hardware by swapping the polarity convention of the differential input.
  • Summing the Z output with a photodiode yields a count of matching bits, which supports binary neural network convolution and hyperdimensional search.
  • The 50 ps write pulse implies memory updates at up to 20 GHz, faster than the electrical SRAM macros the paper compares against.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the energy figure (13.2 fJ/bit) counts optical pulse and electrical driver energy but excludes the thermal tuning power (up to 7.2 mW per ring) the paper cites for fabrication-mismatch correction; amortized over a large array, tuning power could dominate.
  • Editorial inference: since the latch consumes a continuous 10 µW bias laser per cell, a large X-pSRAM array has a static optical power floor that makes energy-per-useful-bit, not energy-per-XOR, the metric that matters at scale.
  • Editorial inference: the same XOR-as-equality structure is exactly the primitive a content-addressable memory needs, so the WDM-summed output could plausibly serve as a match-line detector, an application the paper only gestures at through cosine-similarity estimation.
  • Editorial inference: the paper's 20 GHz write estimate follows directly from the 50 ps pulse, but the hold-state verification in Fig. 3 is short; a longer transient noise or crosstalk study would be a natural test of whether the latch really holds indefinitely.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes X-pSRAM, a photonic SRAM bitcell that combines storage with in-situ Boolean XOR computation. The bitcell uses cross-coupled microring resonators and differential photodiodes for storage, plus two additional rings and an MMI coupler for read and XOR operations. The authors validate the design with GF45SPCLO PDK transient simulations: write/hold/read waveforms in Fig. 3, all four XOR truth-table combinations in Fig. 4, and an 8-wavelength WDM parallel XOR in Figs. 5 and 6. They claim at least 10 GHz read/write/compute operation, a 20 GHz write speed, and 13.2 fJ/bit XOR energy, with WDM enabling n-bit single-shot XOR. The reported functionality is clearly exercised in simulation, but the headline performance numbers rest on isolated-pulse simulations and omit thermal tuning power, so the performance claims are not yet fully supported.

Significance. If the performance claims hold, this is a notable step toward a CMOS-compatible photonic bitcell that simultaneously stores data and performs in-memory XOR, with a plausible WDM scaling path for parallel bitwise operations. The paper’s strengths include a clean truth-table-level verification of all four XOR input combinations, an 8-bit WDM demonstration that matches the expected XOR output, and a concrete PDK-based implementation. The central compute functionality appears independently exercised rather than assumed from prior work. However, the 10/20 GHz speed and 13.2 fJ energy claims are extrapolated from isolated 50/100 ps pulses and from an energy count that excludes thermal tuning, so the significance is currently conditional on additional burst-mode simulation and a more complete energy accounting.

major comments (3)
  1. [Section IV.A and IV.B, Figs. 3 and 4] The 20 GHz write speed and 10 GHz read/compute speed are inferred from 50 ps and 100 ps pulse widths, but pulse width is not cycle time. In the plotted transients, write events occur at approximately 0.8 ns and 1.3 ns (about 500 ps apart, i.e., ~2 GHz), and XOR pulses occur at 1.67, 1.93, 2.67, and 2.93 ns (minimum separation ~260 ps, i.e., ~3.8 GHz). Since the storage element is a regenerative cross-coupled latch, sustained operation at 10 or 20 GHz requires demonstrating that the latch, photodiode currents, and electrical drivers settle to valid states before the next complementary pulse arrives. Please add back-to-back periodic simulations at the claimed rates with measured output margins and bit-error behavior, or revise the speed claims to reflect the demonstrated pulse-based latency rather than throughput.
  2. [Section IV.D, thermal tuning paragraph] The 13.2 fJ/bit energy estimate omits the thermal tuning power that the manuscript itself states can reach up to 7.2 mW per ring. With two latch rings tuned, this DC power alone corresponds to roughly 1.44 pJ/bit at 10 GHz, about two orders of magnitude above the quoted 13.2 fJ. The paper should either include realistic tuning power in the energy-per-bit metric, or explicitly separate static calibration/standby power from active compute energy and justify why the tuning contribution can be neglected at the claimed operating rate. As written, the 13.2 fJ figure is an incomplete representation of the system-level energy cost.
  3. [Abstract and Section II, Fig. 1] The abstract's claim that read, write, and compute operations are 'entirely in the optical domain' is contradicted by the detailed description. The bitcell uses photodiodes to convert light to electrical current, electrical drivers D1/D2, and VDD/GND supplies; the storage nodes Y and YB are electrical. Only the input data waveguides and the output Z are optical. The design is electro-optic, not all-optical. Please revise the wording to 'photonic' or 'electro-optic' and ensure that downstream statements about 'photonic IMC' are consistent with the actual mixed-domain operation.
minor comments (5)
  1. [Figs. 3 and 4] The time and power axes in Figs. 3 and 4 are unlabeled and lack units; adding axis labels and marking the threshold level at the Z output would substantially improve reproducibility of the verification.
  2. [Throughout] The foundry node name is printed inconsistently as 'GF45SPCLO' and '45SPLCO'; please unify the spelling.
  3. [Abstract and Section IV.A] The abstract states at least 10 GHz for read, write, and compute, while Section IV.A claims a 20 GHz write speed; please clarify whether the headline write throughput claim is 10 GHz or 20 GHz and keep the abstract consistent with the detailed results.
  4. [Section III and Fig. 2] The array is described as m x n, with each row assigned a distinct wavelength, but the text refers to an 'n-bit' XOR operation; the bit count is determined by the number of rows (wavelengths) rather than the number of columns, so the notation should be aligned.
  5. [Table I] The area values listed for the SRAM IMC rows, particularly '< 3 × 10^-6' mm^2, appear implausibly small for complete macros; please verify the units and source values or add a footnote explaining the estimate.

Circularity Check

2 steps flagged · score 6.0 of 10

The headline speed and energy figures are the reciprocals and products of the chosen simulation pulse width and power, while the XOR logic itself is independently verified; circularity is partial.

  1. self definitional [Abstract; Section IV-A (Write, Hold, and Read Operation); Section IV-D (Performance Metrics Calculation)]
    "The simulation results demonstrate that the write operation requires only a 50 ps pulse, enabling a memory update speed of up to 20 GHz ... A 100 ps pulse with 100 µW optical power has been utilized to perform the per-bit XOR-compute operation. ... The compute latency per operation is 100 ps (10 GHz)."

    The claimed write speed (20 GHz) and compute speed (10 GHz) are the arithmetic inverses of the chosen simulation stimuli, 1/50 ps and 1/100 ps, respectively. The abstract headline 'at least 10 GHz read, write, and compute operations' is thus the reciprocal of the pulse widths the authors selected, so the reported speed is defined by the input rather than measured as a sustained throughput. No back-to-back operation at 10 or 20 GHz is simulated: in Figs. 3 and 4 the operations are spaced roughly 260–500 ps apart, so a 100 ps (or 50 ps) cycle time is never exercised. The move 'latency per operation = 100 ps' assumes cycle time equals pulse duration, and the resulting '10 GHz' reduces by construction to that assumption.

  2. self definitional [Abstract; Section IV-D (Performance Metrics Calculation)]
    "Each XOR computation utilizes 100 µW input laser power with a 100 ps pulse width. Considering a 10 µW bias laser connected to the IN port, along with electrical energy consumption for photodiode biasing and electrical drivers, the estimated average energy per bit computation is 13.2 fJ (optical: 11 fJ, electrical: 2.2 fJ)."

    The reported per-bit energy is, to first order, the product of the chosen input power and pulse width: 100 µW × 100 ps = 10 fJ plus the 10 µW bias laser × 100 ps = 1 fJ, which is exactly the stated 11 fJ optical component; the remaining 2.2 fJ is an estimate for drivers and biasing. The abstract's 'consumed 13.2 fJ energy per bit for XOR computation' is therefore the test stimulus's own power-time product presented as measured consumption, not an independently predicted value. It also excludes the steady-state thermal tuning cost stated later in the same section (up to 7.2 mW per ring), which at the claimed 10 GHz would amortize to well over a picojoule per bit.

full rationale

The core functional claims are self-contained and non-circular: the in-situ XOR between stored Y and input X is exercised against all four truth-table cases in Fig. 4, and the 8-bit WDM parallel XOR in Fig. 6 reproduces the correct bitwise result (10010011 XOR 11001010 = 01011001). These simulations cover the full bitcell, so the use of the authors' prior pSRAM latch [30] as a building block is not load-bearing for the compute claim; no uniqueness theorem or ansatz is imported from [30], and its behavior is re-simulated here. Where circularity enters is in the headline quantitative metrics. The '20 GHz write' and '10 GHz compute' claims are exact reciprocals of the 50 ps and 100 ps pulses the authors chose to apply (Section IV-A and IV-D), with no back-to-back cycling simulated; the plotted transients show operation gaps of roughly 260–500 ps, so the claimed rate is an extrapolation that reduces by construction to the chosen pulse width. Similarly, the '13.2 fJ/XOR' figure is dominated by the identical chosen inputs (100 µW × 100 ps plus 10 µW × 100 ps gives the report's 11 fJ optical component), and the paper's own stated 7.2 mW per ring thermal tuning power is excluded from the comparison in Table I. These are construction-level reductions of the paper's headline numbers, not of the functional logic. Score 6: one or more 'predictions' reduce by construction, while the core compute behavior retains independently verified simulated content.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The central result is a circuit design validated by simulation. It rests on standard photonic device behavior, prior same-author latch work, and PDK model fidelity. No new physical entities such as particles, forces, or dimensions are introduced. The free parameters are operating points and geometry choices; the most consequential are the optical powers and the WDM tuning step, because the energy and parallel-compute claims are direct products of these values. The 13.2 fJ/bit claim excludes the thermal tuning overhead that the paper itself says can reach 7.2 mW per ring.

free parameters (6)
  • Write pulse power PWR = 1 mW peak, 50 ps pulse
    Chosen so the write photocurrent overcomes the 10 uW bias latch; the write speed and energy claims depend on this operating point.
  • Read and input optical power PX = 100 uW peak, 100 ps pulse
    Used for all read and XOR operations; the optical energy contribution (11 fJ per bit) is the product of this power and pulse width plus the bias laser contribution.
  • Latch bias laser power = 10 uW continuous at 1310.52 nm
    Required for the hold operation; contributes roughly 1 fJ per 100 ps compute event and is part of the 13.2 fJ/bit estimate.
  • Microring geometry: radius and gaps = R = 7.5 um; M1/M2 gaps 180 nm and 395 nm; M3/M4 bus gap 200 nm
    Design parameters that set resonance wavelengths and coupling; the transient simulation results depend on them.
  • WDM dL tuning step = 34 nm per channel, 8 channels in one FSR
    This tuning step is asserted to give distinct resonances with minimal crosstalk, but no crosstalk simulation or measurement is provided.
  • Thermal tuning DC power = up to 7.2 mW per ring, excluded from per-bit energy
    Mentioned as post-fabrication calibration; if required, it would dominate the 13.2 fJ/bit energy claim and is not included in the performance comparison.
assumptions (4)
  • domain assumption A microring resonator couples light to the drop port when on resonance and passes light to the thru port when off resonance.
    Used throughout Section II; the entire read and XOR scheme relies on this switching behavior, and the simulation assumes ideal resonance without crosstalk.
  • domain assumption The cross-coupled arrangement of microrings and photodiodes forms a bistable latch that retains data while VDD and the lambda_IN bias laser are maintained.
    Described in Section II-B and taken from the authors' prior pSRAM work [30]; the present paper uses this latch as a building block rather than re-deriving its stability.
  • domain assumption Varying ring adjustment length dL in 34 nm steps places eight resonances in one free spectral range with minimal inter-channel crosstalk.
    The single-shot 8-bit XOR claim in Section IV-C depends on this tuning assumption; no crosstalk analysis is presented.
  • domain assumption GlobalFoundries 45SPCLO PDK models faithfully reproduce the transient behavior of the microrings, photodiodes, MMI, and drivers at 10 GHz.
    All speed, power, and energy numbers in Section IV are simulation outputs; without hardware validation this remains an untested modeling assumption.

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Cite this review

Pith. "Pith review of X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing." pith.science (2026). https://pith.science/paper/SOHTZARS

@misc{pith2026250622707,
  author       = {Pith},
  title        = {Pith review of: X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SOHTZARS}},
  note         = {Machine review of arXiv:2506.22707}
}
read the original abstract

Traditional von Neumann architectures suffer from fundamental bottlenecks due to continuous data movement between memory and processing units, a challenge that worsens with technology scaling as electrical interconnect delays become more significant. These limitations impede the performance and energy efficiency required for modern data-intensive applications. In contrast, photonic in-memory computing presents a promising alternative by harnessing the advantages of light, enabling ultra-fast data propagation without length-dependent impedance, thereby significantly reducing computational latency and energy consumption. This work proposes a novel differential photonic static random access memory (pSRAM) bitcell that facilitates electro-optic data storage while enabling ultra-fast in-memory Boolean XOR computation. By employing cross-coupled microring resonators and differential photodiodes, the XOR-augmented pSRAM (X-pSRAM) bitcell achieves at least 10 GHz read, write, and compute operations entirely in the optical domain. Additionally, wavelength-division multiplexing (WDM) enables n-bit XOR computation in a single-shot operation, supporting massively parallel processing and enhanced computational efficiency. Validated on GlobalFoundries' 45SPCLO node, the X-pSRAM consumed 13.2 fJ energy per bit for XOR computation, representing a significant advancement toward next-generation optical computing with applications in cryptography, hyperdimensional computing, and neural networks.

Figures

Figures reproduced from arXiv: 2506.22707 by the authors.

Figure 1
Figure 1. Schematic and operational overview of the XOR-augmented photonic SRAM (X-pSRAM) bitcell. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. X-pSRAM Array Architecture for n-bit XOR Computation leveraging [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Verification of the write, hold and read operations in X-pSRAM. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: Resonance wavelength tuning for WDM-based XOR computation. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Verification of 8-bit parallel XOR-compute operation using wavelength-multiplexed X-pSRAM array. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.