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REVIEW 4 major objections 4 minor 63 references

A Flexible Instruction Set Architecture for Efficient GEMMs

T0 review · 4 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims a matrix ISA that stores tiles in the existing vector register file and lets software set tile geometry at runtime outperforms fixed-geometry matrix ISAs like Intel AMX on convolution and transformer GEMMs, with 1.35x…

desk verdict A flexible matrix ISA worth talking about, but the 1.35x headline rests on unvalidated simulation; still deserves review. read the letter →

arxiv 2507.03522 v1 pith:CPOIHENZ submitted 2025-07-04 cs.AR cs.LG

Alexandre de Limas Santana , Adrià Armejach , Francesc Martinez , Erich Focht , Marc Casas This is my paper · ORCID
classification cs.ARcs.LG
keywords matrixinstructionsetarchitectureGEMMvectorregisterfiletilegeometryAMXRISC-VVsystolicarraytransformerinference
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Modern CPUs increasingly add matrix instruction-set extensions to speed up GEMMs, but the paper argues that existing designs--fixed tile geometries and dedicated matrix registers--leave performance on the table for the small, tall, or skinny matrices common in convolution and transformer workloads. It proposes the Matrix Tile Extension (MTE), a matrix ISA that stores matrix tiles in the existing vector register file and lets software program the tile shape (M, N, K) at runtime through a 64-bit control register. Because the ISA is decoupled from the microarchitecture, the same code can run on a long-vector implementation or a systolic-array implementation, and software can use all vector registers for loop unrolling instead of the few dedicated tile registers of current matrix ISAs. On a trace-driven simulator modeling equal peak throughput, MTE is reported to achieve average speedups of 2.67x, 2.45x, 2.3x, and 1.35x over an 8192-bit vector ISA, a 16384-bit vector ISA, a 4x4-tile matrix ISA, and an AMX-style matrix ISA, respectively. The central practical claim is that flexibility in tile geometry plus reuse of the vector register file is worth more than a dedicated fixed-shape matrix unit.

What carries the argument

The load-bearing mechanism is MTE's reinterpretation of the vector register file as matrix tiles plus a runtime-programmable tile geometry held in a 64-bit CSR. The formulas $M = VLEN/RLEN$, $N = RLEN/SEW$, $K = min(M,N)$ (uniform precision) and the transposed-B variant for mixed precision define the largest tile that fully uses a vector register, and the tss instructions grant whatever smaller geometry software requests. On the vector microarchitecture, the tfmul/tmul instructions are decomposed into K cvfma micro-operations: the B operand enters each lane by implicit broadcast, the C operand is laid out lane-locally, and the A operand is shifted across lanes through the lane interconnect; the vector mask and programmable vector length disable inactive rows and columns. On the systolic microarchitecture, the same MTE instructions drive a fixed grid of multiply-accumulate units. This separation of ISA from implementation is what makes the geometry-agnostic claim concrete, and the reuse of the vector register file is what gives software 32 architectural registers instead of AMX's eight tile registers.

What would settle it

Build the MTE32v and MTE32s configurations in RTL (or a cycle-accurate simulator calibrated to a real long-vector core) and measure the actual latency of the tfmul/tmul instructions across the full range of tile shapes; if the measured static plus dynamic cost exceeds the modeled 36-cycle static and active-vector-length-dependent cost, recompute the convolution and transformer speedups against a real AMX baseline and check whether the 1.35x average holds.

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Extended reading notes

Core claim

The paper's central claim is that the rigidity of current matrix ISAs, not their peak throughput, is what makes them deliver suboptimal GEMM efficiency, and that a matrix ISA can be made both flexible and cheap. MTE treats each vector register as a rank-2 tile: with a design-time row length RLEN and runtime element width SEW, a vector register of VLEN bits holds VLEN/RLEN rows of RLEN/SEW elements, and the CSR fields tm, tn, and tk encode the active M, N, and K dimensions. Uniform-precision kernels use a row-major tile interpretation with $M = VLEN/RLEN$, $N = RLEN/SEW$, $K = min(M,N)$; mixed-precision kernels store B transposed so that the wider output type does not waste vector capacity. The tile-multiply instruction is implemented either as a systolic array or as a decomposition into K component vector FMAs (cvfma) on a standard vector processor, using implicit broadcast for the B operand and the lane interconnect to move A elements across lanes. The authors report that this design lets MTE vectorize GEMMs across M, N, and K, retire roughly 14x fewer vector/matrix instructions than the 8192-bit vector baseline, and beat an AMX-semantics configuration by 1.35x on average while requiring only a few new instructions and a 64-bit CSR.

Load-bearing premise

The load-bearing premise is that the simulated microarchitectural costs for the new tile-multiply hardware--the 36-cycle static latency, the vector-length-dependent dynamic latency, and the lane-interconnect flow of A operands--match a real implementation, because only the AMX-like MTE8s configuration was validated against real silicon (median 5% error) and the MTE32 configurations behind the 1.35x claim were not.

Editorial extensions

If this is right

  • If MTE's results hold, a matrix ISA can be added to an existing vector ISA with little extra architectural state, making matrix acceleration available on cores that already have a vector register file.
  • Software and JIT code generators could choose tile geometry at runtime to match each GEMM's M, N, and K, eliminating the layout transposes and memory round-trips that fixed-geometry AMX kernels need for transformer shapes.
  • With 32 architectural registers available to hold A, B, and C tiles, compilers can unroll the M loop more deeply and reuse B tiles more often, which is the mechanism behind the claimed speedups.
  • The same MTE code can target a long-vector implementation and a systolic-array implementation, so hardware vendors could ship either microarchitecture without changing the ISA contract.
  • Mixed-precision GEMMs can use the full vector register length because storing B transposed removes the output-type constraint on N, which matters for bf16-to-fp32 and int8-to-int32 workloads.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the real cost of the lane-interconnect A-operand flow is higher than modeled, the MTE32v advantage over the MTE8s/AMX baseline would shrink; the paper's 1.35x speedup should be read as conditional on the simulator's cost assumptions.
  • The design suggests a broader principle: dedicated matrix register files may be unnecessary, and future matrix extensions could reinterpret existing vector storage, freeing die area for more registers or compute.
  • A direct test of the paper's bottleneck analysis is to simulate AMX with more than eight tile registers; the paper predicts efficiency would rise with register count, which would isolate the register-count effect from the tile-geometry effect.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper proposes the Matrix Tile Extension (MTE), a matrix ISA that reuses vector registers as matrix tiles, defines tile geometry through a 64-bit CSR, and claims to decouple the ISA from the underlying microarchitecture. It describes two possible implementations (one based on a cvfma decomposition in a vector processor, one based on a systolic array), evaluates the designs with a trace-driven simulator, and validates one AMX-compatible configuration (MTE8s) against real Intel AMX hardware on 52 convolutions with a reported median error of 5.0%. The evaluation covers 75 convolution and 18 transformer GEMM workloads, reporting geometric mean speedups of MTE32s over Vector 1KB, Vector 2KB, SiFiveInt, and MTE8s of 2.67x, 2.45x, 2.3x, and 1.35x, respectively, with smaller end-to-end model speedups over MTE8s.

Significance. If the simulated results are reliable, the paper makes a useful contribution to the discussion of CPU matrix ISAs by showing that a geometry-agnostic matrix ISA reusing vector registers can outperform fixed-geometry, dedicated-register matrix ISAs on realistic convolution and transformer workloads. The paper's strengths are its concrete ISA definition, its large workload suite, the use of a JIT-based kernel generator, and the fact that the simulator is anchored to real AMX measurements through the MTE8s configuration. However, the central performance claims rest on microarchitectural latency assumptions for the MTE32v and MTE32s configurations that are not validated against hardware, RTL, or even a sensitivity study, and the comparison to AMX involves a possible precision mismatch. These issues must be addressed before the headline speedup can be accepted.

major comments (4)
  1. [Section IV-A2 and Table VII] The headline speedups of MTE32v and MTE32s over MTE8s (1.16x and 1.35x in Section VI-A) are produced entirely by the trace-driven simulator for configurations that are never validated. Only MTE8s is validated against real AMX hardware (Section V-E, Figure 6). The MTE32v result depends on the modeled cvfma decomposition, in which the A operand moves through the lane interconnect from lane to lane, and the MTE32s result depends on an unvalidated systolic-array latency model. Table VII reports static/dynamic latencies of 36/64 for MTE32v and 36/16 for MTE32s, but the paper does not derive these values from a hardware implementation, RTL, or sensitivity analysis. Because the claimed margin over MTE8s is small, a modest increase in the cvfma broadcast/shuffle cost or the systolic MMA latency could erase or invert the reported speedup. Please add a sensitivity study varying these parameters, or validate at least one of the MTE32 configurations against an RTL/FPGA implementation.
  2. [Sections V-B2, V-C, and Figure 9] The AMX comparison appears to compare different precisions. The paper states that the convolution workloads use 32-bit floating-point datatypes (Section V-B2), but Section II-C1 states that AMX TMUL supports only bf16-to-fp32 floating-point operations, not fp32 inputs. Figure 2 plots AMX efficiency against a bf16 peak while the simulated MTE approaches are evaluated at a 512 SP FLOP/cycle fp32 peak (Section V-A). If AMX executes bf16 and MTE executes fp32, then the reported 1.29x-1.35x speedups are not iso-precision and may partly reflect a data-type advantage rather than an ISA-efficiency advantage. Please clarify whether the AMX runs use the same fp32 inputs as the other approaches, and if conversions to bf16 are used, state this explicitly and discuss the precision implications.
  3. [Abstract and Section VI-A] The abstract and conclusion describe the 1.35x figure as a speedup over the best state-of-the-art matrix ISA (AMX), but the number is actually a geometric mean speedup of MTE32s over MTE8s, a simulated configuration that reproduces AMX semantics on a different modeled microarchitecture. The only direct comparison to measured AMX is Figure 9, which covers convolutions and reports a 1.29x speedup for MTE32v. The manuscript should state clearly in the abstract and conclusions that the headline speedup is relative to a simulated AMX-semantic baseline, and should either report measured AMX results for the full workload set or provide a quantitative argument that MTE8s faithfully captures AMX performance for the transformer and large-OC workloads as well.
  4. [Section V-E and Figure 6] The simulator validation is limited to 52 convolutions with output-channel counts up to 256, and it does not cover the transformer GEMM workloads or the larger categories in Figure 7 where the largest MTE gains appear. The end-to-end results in Figure 8 show the highest MTE32s speedups for BERT and GPT-2 (1.20x and 1.22x), yet no measured AMX or MTE8s data are provided for transformer GEMMs. A median error of 5.0% on small-OC convolutions does not establish simulator accuracy for the workload classes that drive the paper's main end-to-end claims. Please extend the validation to transformer GEMMs or explicitly bound the simulator uncertainty for those workloads.
minor comments (4)
  1. [Section VI-A2] The text refers to the '8084+ processor'; this should be '8480+'.
  2. [Section IV-C] There are several typos, including 'discuses' for 'discusses' and 'implementetion' for 'implementation'.
  3. [Section III-B and III-C1] The CSR table lists ttype[i,o] as 8 bits with two 4-bit fields, but Section III-C1 describes the ttypeio immediate as 3 bits; please clarify how the 3-bit immediate maps to the two 4-bit fields.
  4. [Section V-D] The area analysis in Table VIII reports register-file areas but does not include the systolic-array area for MTE8s and MTE32s; since Table VI describes the systolic array as a separate accelerator, please either include its area contribution or state why it is omitted.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the performance claims are simulation-based with an externally anchored baseline, and the ISA geometry formulas are definitions rather than fitted predictions.

full rationale

The paper's central claims are architectural simulation results, not results derived from fitted parameters or self-referential definitions. The baseline is anchored externally: the MTE8s configuration reproduces AMX semantics and is validated against real AMX hardware on an Intel Xeon Platinum 8480+, with a median error of 5.0% (Section V-E, Figure 6). The headline speedups of MTE32v and MTE32s over MTE8s arise from modeled architectural differences, specifically a larger number of architectural registers enabling more loop unrolling, and these outcomes are reported as simulation results rather than as quantities fit to the workloads. The tile-dimension equations (Formulas 1-3 in Section III-A) define the maximum geometry achievable given VLEN, RLEN, and SEW; they are identities following from the definitions of ROWS and COLS, not empirical predictions, and no claim is made that they 'predict' external data. Self-citations such as [4] for direct convolution kernel recipes are methodology references, not load-bearing uniqueness arguments, and they do not contain or presuppose the paper's speedup conclusions. The unvalidated status of the MTE32v and MTE32s microarchitectural models (notably the cvfma lane-interconnect cost) is a correctness or validation concern, not circularity: the simulator's cost assumptions are stated explicitly in Table VII and Section IV-A2, and the results would be falsifiable by RTL or hardware measurements. No equation-level reduction of a target result to its inputs, and no fitted-input-renamed-as-prediction pattern, is present.

Assumptions & free parameters 4 free parameters · 5 assumptions · 2 invented entities

The central performance claims rest on a small set of hand-chosen simulator and configuration parameters rather than on fitted constants: static latencies, normalized peak throughput, RLEN, and physical register file sizes. The MTE ISA and its cvfma microarchitecture are invented proposals whose only evidence is simulation; the AMX baseline is the one externally anchored component. The energy and area results inherit the assumptions of McPAT/PCACTI.

free parameters (4)
  • MTE/SiFiveInt instruction static latency = 36 cycles (MTE); 28 (SiFiveInt); 20 (vector)
    Hand-chosen front-end latencies in Table VII. The 36-cycle value is applied to both MTE8s and MTE32s/32v, so it partially determines the MTE speedups. No sensitivity analysis is provided.
  • Normalized peak throughput = 512 FLOP/cycle for all evaluated approaches
    Section V-A sets all ISAs, including the AMX model, to the same 512 FLOP/cycle peak. This is a deliberate methodology choice to isolate ISA effects, but it means the 1.35x is an ISA-efficiency speedup, not a comparison of real chips with their actual AMX peak.
  • RLEN (matrix row size) = 512 bits for MTE8s, MTE32v, MTE32s; 2048 bits for SiFiveInt emulation
    Design-time constant in Formulas 1-3 that sets the GEMM tile shape (16x16x16 for fp32). The choice matches AMX's 512-bit row size; other RLEN values would change the results.
  • Physical register file sizes = 24 x 1KB physical (MTE8s), 40 x 1KB (MTE32v/s)
    Section V-C assigns MTE8s only 24 physical registers to reproduce AMX's 8 architectural tiles, while MTE32 variants get 40. The 1.35x gain is largely attributed to this register-count difference, which is a modeling choice about how much renaming the MTE implementations need.
assumptions (5)
  • domain assumption RISC-V V vector length agnostic model (vsetvl, vector masks, predication) works as specified across the evaluated configurations.
    Section III-C4 and Algorithm 1 rely on vsetvl and tvmask to hide inactive rows and columns; the simulator takes these costs as given.
  • ad hoc to paper MMA instructions can be decomposed into cvfma vector micro-operations with the modeled dataflow (B broadcast, A via lane interconnect) at the stated throughput.
    Section IV-A2 describes the cvfma scheme; its cycle counts and interconnect costs are assumed, not measured.
  • domain assumption The trace-driven simulator's static-plus-dynamic latency model captures the performance of both vector and systolic implementations.
    Section V-E defines the model; it is validated only for MTE8s/AMX, not for the MTE32v/MTE32s designs.
  • domain assumption The oneDNN-based AMX kernels and the authors' rvjit-generated kernels are comparably optimized.
    Section V-C compares vendor-tuned AMX (oneDNN v3.5 within PyTorch) against kernels generated by the authors' own JIT assembler; unequal tuning would bias the comparison.
  • domain assumption McPAT/PCACTI at 5nm provide accurate area and energy estimates.
    Section V-D is the basis for the area and energy claims (Tables VIII, Figure 10).
invented entities (2)
  • Matrix Tile Extension (MTE) ISA
    purpose: Adds geometry-agnostic matrix instructions (tss, tl/ts, tfmul/tmul, tvmask) that store tiles in the existing vector register file and configure tile shape via a 64-bit CSR.
    The central proposal; its performance evidence is the authors' own simulator, validated only for the AMX-semantics subset (MTE8s). No silicon or external implementation exists.
  • Component Vector Fused-Multiply-Accumulate (cvfma) micro-instruction
    purpose: Implement each MTE MMA as a sequence of vector FMA micro-ops with lane-local B broadcast and an inter-lane A operand flow.
    A microarchitectural mechanism introduced in Section IV-A2 with assumed costs; no real hardware demonstration.

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Cite this review

Pith. "Pith review of A Flexible Instruction Set Architecture for Efficient GEMMs." pith.science (2026). https://pith.science/paper/CPOIHENZ

@misc{pith2026250703522,
  author       = {Pith},
  title        = {Pith review of: A Flexible Instruction Set Architecture for Efficient GEMMs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CPOIHENZ}},
  note         = {Machine review of arXiv:2507.03522}
}
read the original abstract

GEneral Matrix Multiplications (GEMMs) are recurrent in high-performance computing and deep learning workloads. Typically, high-end CPUs accelerate GEMM workloads with Single-Instruction Multiple Data (SIMD) or vector Instruction Set Architectures (ISAs). Since these ISAs face significant issues when running GEMM workloads, particularly when dealing with small, tall, or skinny matrices, matrix ISAs have been proposed and implemented by major hardware vendors in the last years. Although these matrix ISAs deliver larger throughput when running GEMMs than their SIMD/vector counterparts, they are rigid solutions unable to dynamically adapt themselves to application-specific aspects like the data format. This paper demonstrates that the state-of-the-art matrix ISAs deliver suboptimal performance when running the most commonly used convolution and transformer models. This paper proposes the Matrix Tile Extension (MTE), the first matrix ISA that completely decouples the instruction set architecture from the microarchitecture and seamlessly interacts with existing vector ISAs. MTE incurs minimal implementation overhead since it only requires a few additional instructions and a 64-bit Control Status Register (CSR) to keep its state. Specifically, MTE can i) vectorize GEMMs across the three dimensions M, N, and K; ii) leverage the capacity of the existing vector register file; and iii) decouple the tile shape from the underlying microarchitecture. MTE achieves speed-ups of 1.35x over the best state-of-the-art matrix ISA.

Figures

Figures reproduced from arXiv: 2507.03522 by the authors.

Figure 1
Figure 1. Structure of the i-th lane of a vector unit with N lanes. The vector register file storage is interleaved across the N lanes. Functional units contain one execution pipeline per lane operating on local elements across V L/N steps. The lane interconnect enables communication between lanes. of the number of active rows and the row size in bytes, by populating a 64-byte CSR using a dedicated instruction. The AMX TMUL u… view at source ↗
Figure 3
Figure 3. Rank-1 (left) and rank-2 (right) interpretations of the vector register [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Vector processing of matrices in vector registers. White and dark [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (5 more)
Figure 5
Figure 5. Figure 5: Operand buffers contents within one vector lane during a matrix [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 6
Figure 6. Figure 6: Measured and simulated performance of convolution dataset on an [PITH_FULL_IMAGE:figures/full_fig_p010_6.png]
Figure 7
Figure 7. Figure 7: Percentage of the peak performance (efficiency) obtained by convolution and GEMM kernels. Convolution and GEMM workloads are displayed in [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]
Figure 8
Figure 8. Figure 8: Application-level speedup of MT E32v and MT E32s, considering computer vision and language models. 32 64 128 256 512 # of output feature maps 0% 20% 40% 60% 80% 100% Efficiency (%) AMX MTE32v [PITH_FULL_IMAGE:figures/full_fig_p011_8.png]
Figure 9
Figure 9. Figure 9: Convolution efficiency obtained by AMX compared to MTE [PITH_FULL_IMAGE:figures/full_fig_p011_9.png]

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