Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search

Carlos H. Diaz; Chang Eun Song; Gert Cauwenberghs; Gopabandhu Hota; Haichao Yang; Keming Fan; Kerem Akarvardar; Leo Liu; Meng-Fan Chang; Mingu Kang

REVIEW 3 major objections 4 minor 15 references

Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search

T0 review · 3 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read Clo-HDnn is a fabricated 40 nm accelerator that runs continual learning end to end with hyperdimensional computing, avoiding gradient-based training.

desk verdict A credible fabricated-chip result in HDC continual learning, marred by an unmeasured accuracy claim for progressive search. read the letter →

arxiv 2507.17953 v1 pith:74MMAXNA submitted 2025-07-23 cs.AR cs.LG

Chang Eun Song , Weihong Xu , Keming Fan , Soumil Jain , Gopabandhu Hota , Haichao Yang , Leo Liu , Kerem Akarvardar

show 5 more authors

Meng-Fan Chang Carlos H. Diaz Gert Cauwenberghs Tajana Rosing Mingu Kang

This is my paper · ORCID

classification cs.ARcs.LG

keywords hyperdimensionalcomputingcontinuallearningon-deviceacceleratorprogressivesearchKroneckerHDencoderweightclusteringfeatureextractorgradient-freetrainingenergyefficiency

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports a fabricated 40 nm chip, Clo-HDnn, built to show that continual learning can run entirely on device using hyperdimensional computing (HDC) instead of gradient-based backpropagation. The chip encodes inputs into high-dimensional hypervectors, stores knowledge as class hypervectors that are updated by simple additions and subtractions, and classifies by similarity search. Two mechanisms keep the cost down: a dual-mode datapath that bypasses the feature extractor for easy datasets, and a progressive search that encodes and compares only partial 64-bit hypervector segments when the distance margin already separates classes. Measured on the fabricated chip, the feature extractor reaches 4.66 TFLOPS/W and the hyperdimensional classifier 3.78 TOPS/W, which the paper states as 7.77x and 4.85x higher energy efficiency than state-of-the-art on-device learning accelerators. The paper further states that this is the first chip to support end-to-end continual learning for HDC tasks.

What carries the argument

The load-bearing mechanism is the Kronecker HD encoder combined with progressive partial-hypervector search. The Kronecker structure decomposes the projection into two reshaped block matrix multiplications, turning binary-INT encoding into additions and shrinking encoder memory relative to earlier cyclic random projection schemes; progressive search then encodes and compares only the first 64-bit segments of the query and class hypervectors, using a margin check against thresholds (Th=32 or 64) to decide whether early termination is safe. This partial-search design is what reduces cache storage and complexity, and it is the piece on which the claimed negligible accuracy loss depends.

What would settle it

Run the ISOLET and UCIHAR benchmarks on the chip with progressive search at Th=32 and Th=64 and record accuracy against full-hypervector inference; if the accuracy gap exceeds the negligible loss the paper claims, the early-termination criterion is not trustworthy.

Watch

Extended reading notes

Core claim

Clo-HDnn's central claim is that a complete continual-learning pipeline, spanning feature extraction, encoding, training, inference, and knowledge retention, can be implemented on a single chip with hyperdimensional computing and without gradient descent. The design combines a weight-clustered CNN feature extractor (WCFE) with a Kronecker HD encoder and a hyperdimensional classifier whose class hypervectors are updated in a single pass by adding or subtracting the encoded query depending on correctness, so new tasks do not overwrite earlier classes. For inference, the chip can run in normal mode through the WCFE for hard datasets such as CIFAR-100, or bypass the WCFE entirely for simpler datasets such as ISOLET and UCIHAR. Within the HD module, progressive search fetches only the 64 most significant bits of each class hypervector, computes a partial distance, and stops when the margin between classes exceeds a confidence threshold, cutting search complexity by up to 61% with what the paper calls negligible accuracy loss. The authors state that Clo-HDnn is the first chip to support end-to-end continual learning for HDC tasks.

Load-bearing premise

Progressive search assumes that the distance margin computed from a partial 64-bit hypervector segment reliably predicts the full-hypervector classification at the chosen thresholds; if margins overlap across classes, early termination would cause misclassifications.

Editorial extensions

If this is right

Continual learning on edge devices can avoid backpropagation entirely, with training reduced to single-pass hypervector additions and subtractions.
Datasets with easy inputs can skip the feature extractor, so the energy cost of a deployed model can be cut substantially when most queries are simple.
Progressive search means the associative memory for class hypervectors stores partial vectors, reducing both cache size and bandwidth during inference.
The custom ISA makes the same silicon programmable across WCFE, HDC, and FIFO dataflow, so one chip can serve different continual-learning workloads.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the margin-based early termination generalizes, the same progressive principle could be applied at coarser granularities, such as 32-bit segments for simpler data, without retraining, trading a little accuracy for lower latency on the fly.
Because the WCFE accounts for 94.2% of total energy consumption, the main bottleneck for harder image tasks remains feature extraction; a natural next step is a WCFE with clustered weights plus a learned policy for choosing normal versus bypass mode per input.
Since class hypervectors are updated additively, Clo-HDnn's training path is a candidate substrate for online learning from non-stationary streams, but the paper does not report experiments on task-order drift or class imbalance; testing those would clarify how far the forgetting resistance holds.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: the chip is real, the efficiency numbers are credible, and the integration of Kronecker encoding, weight-clustered feature extraction, dual-mode operation, and a custom ISA on a fabricated 40nm part is a reasonable step forward in on-device continual learning with HDC. The soft spot is the progressive-search accuracy claim, which is asserted but never measured at the thresholds actually used.

What's genuinely new is the system-level integration and the measured results. The Kronecker encoder is from their own prior work [13], but combining it with WCFE, a bypassable feature extractor, progressive search, and a programmable instruction set is new. The chip demonstrably runs end-to-end CL on CIFAR-100, ISOLET, and UCIHAR with accuracy close to a floating-point baseline. The measured 4.66 TFLOPS/W and 3.78 TOPS/W at 0.7-1.2V are plausible for a 40nm CMOS design, and the WCFE's weight clustering and pattern reuse is a sensible way to reduce convolution cost.

The main problem is that the 'negligible accuracy loss' from progressive search is unquantified. Section 'Proposed Design' says thresholding partial Hamming distances reduces complexity by up to 61%, but the paper never reports accuracy at the chosen thresholds Th=32 or 64. Figure 9 compares the full system to a floating-point baseline but does not break out full-search versus progressive-search accuracy. So the complexity reduction is advertised without the accuracy cost. It's possible the system was always run with progressive search and Fig.9 already includes that cost, but the text doesn't say so. This is a load-bearing omission because the confidence-threshold mechanism is a headline feature. It's easily fixed with an accuracy-versus-threshold plot.

Minor issues: the 'first chip' claim rests on a narrow comparison table; a broader survey of HDC accelerators would strengthen it. The energy-efficiency scaling methodology to 40nm could be more detailed. No code or data release, but that's normal for hardware papers.

This is an engineering contribution, not a new scientific principle, but it's a credible one. The architecture is coherent and the measured silicon speaks for itself. The missing progressive-search accuracy is the only real blocker. With that one figure, the paper would be solid.

Recommendation: send to peer review. A serious referee can verify the claims and request the accuracy data. Not a desk reject.

Referee Report

3 major / 4 minor

Summary. The paper presents Clo-HDnn, a 40 nm CMOS accelerator for on-device continual learning (CL) using hyperdimensional computing (HDC). The chip combines a weight-clustering CNN feature extractor (WCFE), a Kronecker-product HD encoder, a gradient-free HD training/inference module, and a custom ISA. Two notable architectural mechanisms are a dual-mode operation that bypasses the WCFE for simple datasets and a progressive search that encodes and compares only partial 64-bit segments of the query and class hypervectors, terminating when the distance margin exceeds a threshold. Measured silicon results show peak energy efficiencies of 4.66 TFLOPS/W (WCFE) and 3.78 TOPS/W (HDC), corresponding to 7.77x and 4.85x improvements over selected prior accelerators, and the paper claims to be the first chip supporting end-to-end CL for HDC tasks.

Significance. If the claims hold, Clo-HDnn is a valuable measured demonstration of an HDC-based continual on-device learning accelerator. Its strengths include fabricated-chip results, measured energy efficiency across voltage/frequency, a concrete Kronecker encoder implementation, and a practical gradient-free training flow with class hypervectors. The paper also makes falsifiable claims about progressive-search complexity reduction and dual-mode feature-extractor bypass. However, the most novel efficiency claim—61% complexity reduction with 'negligible accuracy loss'—is not supported by any accuracy measurement at the actual thresholds used, and the 'first chip' claim is based on a narrow comparison table. These gaps are load-bearing for the central claims and must be addressed.

major comments (3)

[Proposed Design, Fig.4; Performance Results, Fig.9] The claim of 'negligible accuracy loss' from progressive search is not quantified anywhere in the manuscript. Fig.4 reports complexity reductions of 61% (ISOLET, D=2048, Th=32) and 57% (UCIHAR, Th=32), but Fig.9 shows only end-to-end CL accuracy without specifying whether progressive search was enabled or disabling it, and no accuracy-versus-threshold sweep (e.g., Th=16, 32, 64, full) is provided. Because a 64-bit partial Hamming distance is an unbiased but high-variance estimate of the full-distance margin, early termination could systematically misclassify samples with small full margins; the claimed complexity reduction may come at an unstated accuracy cost. Please report accuracy (and, ideally, per-session accuracy) for Th=32, Th=64, and full search on all three benchmarks.
[Performance Results, Fig.11 comparison table] The statement that Clo-HDnn is 'the first chip to support end-to-end CL for HDC tasks' is supported only by the five-row comparison table in Fig.11. That table is too narrow to establish a literature-wide 'first' claim, especially since there are other HDC and CL accelerators not listed. Please either temper the claim to 'among the accelerators compared here' or provide a more systematic related-work survey. In addition, the 'Scaled EE' values in the table are used to compute the 7.77x/4.85x efficiency gains, but no scaling methodology (e.g., technology, voltage, frequency, and precision scaling factors) is given; without that formula the efficiency comparison cannot be reproduced or verified.
[Proposed Design, Fig.4; Performance Results, Fig.9] The dual-mode bypass claim (S1.c) is not directly validated. ISOLET and UCIHAR are only evaluated in bypassing mode, and CIFAR-100 only in normal mode. There is no accuracy comparison between bypassing and normal modes for the same dataset, so the reader cannot judge what accuracy, if any, is sacrificed for the large WCFE energy/latency reduction (94.2% and 87.7%) attributed to bypassing. Please provide accuracy for these datasets with and without WCFE enabled.

minor comments (4)

[Throughout] The terms 'WCFE' and 'FE' are used interchangeably (e.g., abstract says '4.66 TFLOPS/W (FE)' while the text mostly uses 'WCFE'); please unify the terminology.
[Fig.5] The '1376x memory capacity savings' figure is presented without specifying which baseline (RP, cRP, or ID) it is measured against; please clarify whether it is the best or worst baseline and give the exact comparison.
[Fig.2 and Fig.4 captions] There are several typographical errors in the figures: 'ineBicient' should be 'inefficient', 'Di3icult' should be 'Difficult', and 'ID-LEVEL (ID) [12]' is an unusual label that should be expanded or defined.
[Performance Results, Fig.11] The abbreviation 'CIM' (compute-in-memory) and 'ReRAM' are used in the comparison table without definition in the text; please add a brief explanation for readers outside the memory-computing subfield.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: Clo-HDnn is a measured silicon demonstration; the progressive-search approximation is an unverified accuracy claim, not a derivation that reduces to its inputs.

full rationale

The paper's central claims are empirical: energy efficiency (4.66 TFLOPS/W, 3.78 TOPS/W), accuracy versus an FP baseline (Fig. 9), and comparison to prior accelerators are measured on a fabricated 40 nm chip rather than derived from a fitted model. The only self-citation is [13] (W. Xu et al., ICCD 2023) for the Kronecker HD encoder, which is used as a building block and is externally published prior engineering work; it is not a fitted parameter, not a uniqueness theorem, and not an ansatz that the present paper uses to force its conclusions. The progressive-search mechanism (Fig. 4) is an approximation: it terminates when the partial-HV distance margin exceeds a threshold. The paper claims "reducing complexity by up to 61% with negligible accuracy loss," but it never reports accuracy at Th=32 or Th=64, so the "negligible accuracy loss" part is unsupported. That is a completeness/correctness gap, not circularity: the complexity reduction is computed from the stopping rule, and the accuracy claim is an empirical hypothesis that could be falsified by measurement; neither is equivalent by construction to the paper's inputs. No equation is defined in terms of the result, no fitted parameter is renamed as a prediction, and no load-bearing conclusion rests solely on a self-citation. Hence the appropriate finding is no significant circularity (0).

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

The paper introduces no new physical or conceptual entities; it is a hardware architecture. The free parameters are the hand-chosen threshold and hyperdimension design choices. The domain assumptions are standard for HDC and chip acceleration but are not independently verified with ablations.

free parameters (2)

Progressive search confidence threshold (Th) = 32 or 64 (per dataset)
Hand-chosen per dataset; the 'up to 61% complexity reduction with negligible accuracy loss' claim depends on this threshold, but the accuracy loss at Th=32 is not reported for the benchmarks shown.
Hyperdimension D = 1024-8192 (range per dataset)
HD dimension is a design choice affecting the accuracy and efficiency trade-off; the paper uses D=2048 for ISOLET/UCIHAR and D=1024 for CIFAR-100, but does not justify the choice as optimal.

assumptions (5)

standard math Standard properties of Kronecker products (decomposition of encoding into smaller matrix multiplications)
Used in Fig.5 to justify the Kronecker HD encoder's computational savings.
domain assumption HDC class hypervectors are approximately orthogonal, enabling classification and continual learning
The entire approach assumes that class hypervectors can be distinguished by distance, which underlies the inference and training flow (Fig.2, Fig.6).
domain assumption Weight clustering after training preserves CNN feature extractor accuracy
The WCFE relies on post-training clustering of weights (Fig.7) and assumes the resulting accuracy drop is negligible; no ablation is shown.
domain assumption Simple datasets (ISOLET, UCIHAR) can be classified directly from raw features without the CNN feature extractor
The dual-mode bypass assumes that the HD classifier alone is sufficient for these datasets, which is validated only by the reported accuracy results (Fig.9).
domain assumption Progressive search using partial hypervectors yields distance margins that correlate with full-hypervector accuracy
The early termination in progressive search (Fig.4) assumes that the partial distance margin is a reliable confidence measure; this is not proven or quantified.

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Cite this review

Pith. "Pith review of Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search." pith.science (2026). https://pith.science/paper/74MMAXNA

@misc{pith2026250717953,
  author       = {Pith},
  title        = {Pith review of: Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient Hyperdimensional Computing via Progressive Search},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/74MMAXNA}},
  note         = {Machine review of arXiv:2507.17953}
}

read the original abstract

Clo-HDnn is an on-device learning (ODL) accelerator designed for emerging continual learning (CL) tasks. Clo-HDnn integrates hyperdimensional computing (HDC) along with low-cost Kronecker HD Encoder and weight clustering feature extraction (WCFE) to optimize accuracy and efficiency. Clo-HDnn adopts gradient-free CL to efficiently update and store the learned knowledge in the form of class hypervectors. Its dual-mode operation enables bypassing costly feature extraction for simpler datasets, while progressive search reduces complexity by up to 61% by encoding and comparing only partial query hypervectors. Achieving 4.66 TFLOPS/W (FE) and 3.78 TOPS/W (classifier), Clo-HDnn delivers 7.77x and 4.85x higher energy efficiency compared to SOTA ODL accelerators.

Figures

Figures reproduced from arXiv: 2507.17953 by the authors.

**Figure 4.** Fig.4. Data flow of Clo-HDnn’s dual-mode processing and pro [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗

**Figure 5.** Fig.5. Details of proposed kronecker HD encoder and its benefits [PITH_FULL_IMAGE:figures/full_fig_p002_5.png] view at source ↗

Figures from the paper (3 more)

**Figure 7.** Figure 7: Fig.7. (a) Post-training weight clustering of filters, (b) pattern [PITH_FULL_IMAGE:figures/full_fig_p003_7.png]

**Figure 9.** Figure 9: Fig.9. Accuracy results of bypassing WCFE ((a) ISOLET & (b) [PITH_FULL_IMAGE:figures/full_fig_p003_9.png]

**Figure 11.** Figure 11: Fig.11. Chip die photo, Clo-HDnn summary table, and compari [PITH_FULL_IMAGE:figures/full_fig_p003_11.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

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X. Ma et al., MobiCom, 2023, Article 83, 1-15

work page 2023

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Karunaratne et al., ESSCIRC, 2022, pp

G. Karunaratne et al., ESSCIRC, 2022, pp. 105-108

work page 2022

[4] [3]

Prabhu, et al., JSSC, vol

K. Prabhu, et al., JSSC, vol. 57, no. 4, pp. 1013-1026, 2022

work page 2022

[5] [4]

Yang et al., ESSERC, 2024, pp

H. Yang et al., ESSERC, 2024, pp. 33-36

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Yu et al., IPSN, 2024

X. Yu et al., IPSN, 2024

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I. Kazi et al., TCAS-I, vol. 61, no. 11, pp. 3155-3164, 2014

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