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REVIEW 2 major objections 5 minor 1 cited by

A Global-Local Optimization Approach for Asynchronous SAR ADC Design

T0 review · 2 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A two-stage optimizer sizes asynchronous SAR ADCs as complete systems, and all 12 of its 65-nm validation designs met their targets, with SNDR up to 72.2 dB and 177.3 dB Schreier FoM.

desk verdict Useful global-local sizing flow for SAR ADCs, but the headline SNDR/FoM numbers rest on an unvalidated time-interleaved simulation that only works at fs/M as described. read the letter →

arxiv 2507.19541 v1 pith:62FREGNC submitted 2025-07-23 math.OC

Yijia Hao , Ken Li , Miguel Gandara , Shaolan Li , Bo Liu This is my paper · ORCID
classification math.OC
keywords SARADCanalogdesignautomationICsizingglobaloptimizationlocalsurrogatemodelingdifferentialevolutiontime-interleavedsimulation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a successive-approximation-register analog-to-digital converter (SAR ADC) can be sized automatically at the system level, rather than block by block, by splitting the search into a cheap global exploration stage and a more expensive local refinement stage. The authors derive design constraints directly from the target bit count with formulas for step-size ratio error, sampling error, and thermal noise, removing the usual manual step of allocating specifications to individual blocks. In the local stage, a phase-shifted, time-interleaved parallel simulation evaluates SNDR cheaply enough to sit inside an optimization loop. Across 12 design cases in a 65-nm CMOS process, covering 7- and 12-bit converters from 100 kHz to 250 MHz, every case met its derived specification, with the best at 72.2 dB SNDR and 177.3 dB Schreier FoM. This matters because this kind of automation could replace much of the iterative manual tuning that dominates SAR ADC development time.

What carries the argument

The load-bearing mechanism is a two-stage optimization loop with a new simulation trick inside it. First, specifications are generated by formulas: each bit's step-size ratio error obeys $\mathrm{SSRE}_i = |\mathrm{step}_i/\mathrm{step}_{i+1} - 2| < 1/(2^{N-i-1}\sqrt{12N})$ up to the scaling factor $\alpha$, while sampling error, thermal noise, and total error power are budgeted against the quantization-noise floor. Second, the global stage combines differential evolution with an ANN surrogate and infill sampling, scoring candidates with parallel single-point transient tests that measure sampling error, step ratios, and noise. Third, the local stage is a Hooke-Jeeves pattern search with a blended objective that mixes cheap evaluations with periodic expensive SNDR checks; those checks use the paper's proposed time-interleaved parallel transient simulation, in which $M$ simulations at $f_{\mathrm{s}}/M$ with phase-shifted input sine waves are interleaved into a full-rate output record for FFT-based SNDR extraction. That interleaving is what makes accurate SNDR evaluation cheap enough to embed in an optimization loop.

What would settle it

Run a conventional full-rate transient and coherent FFT on the same 12-bit, 20 MS/s design that reports 72.2 dB SNDR and compare it with the phase-interleaved evaluation; disagreement beyond about 1 dB, or a spur that the interleaved spectrum hides, falsifies the fast SNDR claim. A tape-out measurement of that design would settle the question definitively.

Watch

Extended reading notes

Core claim

The central claim is that the whole converter's sizing problem—bootstrap switch, binary-weighted capacitive digital-to-analog converter (C-DAC), dynamic comparator, and SAR logic—can be solved as one constrained optimization. The global phase uses differential evolution with an ANN-based surrogate and infill sampling, judging candidates with cheap single-point transient tests whose error constraints are generated automatically from the resolution N and a user-controlled scaling factor α. The local phase fixes converged variables and applies a blended Hooke-Jeeves pattern search, periodically running a full-sine-wave SNDR check accelerated by phase-shifted, time-interleaved parallel transient simulations. In the paper's strongest validated case, a 12-bit 20 MS/s design, the framework reports 72.2 dB SNDR, 89.3 dB SFDR, 11.7 effective bits, a 4.6 fJ/conversion-step Walden FoM, and 177.3 dB Schreier FoM, with all 12 cases satisfying their automatically derived specifications.

Load-bearing premise

The load-bearing premise is that the phase-shifted, time-interleaved parallel simulations reconstruct the ADC's true output spectrum as faithfully as a full-rate transient simulation would, because the reported SNDR, FoM, and the competitiveness claim all depend on that spectral estimate.

Editorial extensions

If this is right

  • The authors state the framework is technology- and architecture-independent: switching to another CMOS node or another SAR topology changes user inputs such as PDK and topology, not the optimization machinery.
  • Because specifications are derived from top-level requirements rather than allocated by hand, retargeting to a new speed or resolution changes only the user inputs.
  • The $\alpha$ scaling knob tightens or relaxes the derived error budgets, giving a simple way to trade SNDR against power inside the automated flow.
  • The time-interleaved SNDR evaluation gives a speed-up proportional to the number of parallel simulations $M$, which is what makes system-level optimization tractable at 12-bit resolution.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the interleaved simulation is as accurate as claimed, its use extends beyond optimization: any ADC verification loop that needs repeated FFT-based spectral checks could adopt the same phase-shifted parallelism and cut transient simulation time by a factor of $M$.
  • The equal-per-bit error budget is a conservative choice; allocating more budget to early bits and less to late bits could push achievable SNDR closer to or beyond the $6.02N - 4.25$ dB ceiling used in the derivation.
  • Because all 12 validation cases are pre-layout, the cleanest test of the competitive-performance claim is a tape-out of one optimized 12-bit design to see how much layout parasitics and process variation degrade the reported SNDR and FoM.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper presents a two-stage global-local optimization framework for sizing asynchronous SAR ADCs. In the global stage, top-level specifications are automatically derived from a first-principles noise-budget model involving step-size ratio error (SSRE), sampling error, thermal noise, and power, and the design space is explored by an ANN-assisted differential evolution optimizer. In the local stage, a blended Hooke-Jeeves pattern search with selective rollback refines the remaining design variables, using a proposed phase-shifted, time-interleaved parallel transient simulation to accelerate SNDR evaluation. The authors validate the methodology in a 65-nm CMOS process on 12 design cases covering 7- and 12-bit resolutions and sampling rates from 0.1 MS/s to 250 MS/s, reporting SNDR up to 72.2 dB and FoM_S up to 177.3 dB, and compare these pre-layout results with prior measured and post-layout SAR ADC designs.

Significance. If the reported SNDR and FoM values are reliable, the framework is a useful contribution to analog sizing automation: it treats the SAR ADC as a system rather than as isolated blocks, derives constraints from a consistent quantization-noise budget, and runs in roughly six hours on a 32-core machine. A clear strength is that the noise-budget algebra in Eqs. (2)-(11) is internally consistent and the achieved SNDR (72.2 dB) exceeds the derived 68 dB floor, so the result is not forced by construction. The range of demonstrated cases and the low manual effort are also praiseworthy. However, the central performance claim rests on the unvalidated interleaved SNDR extraction in Section III-D and on a Table II comparison that mixes pre-layout simulation with measured and post-layout results; both issues must be resolved before the headline numbers can be accepted.

major comments (2)
  1. [Section III-D] The phase-shifted, time-interleaved transient method is not mathematically equivalent to a single full-rate transient unless the input frequency satisfies f_in/f_s ≡ 1/M (mod 1). The time shift Δt_k = T_in·k/M makes the k-th slow simulation's samples equal to full-rate samples at indices rM+k only when f_in·k/f_s ≡ k/M (mod 1) for every k; otherwise the interleaved record corresponds to a different set of sampling instants and does not reconstruct the true full-rate spectrum. The manuscript never states the input frequencies used in the 12 design cases and never compares the proposed SNDR extraction against a conventional full-rate transient simulation. Since the headline SNDR and FoM values in Fig. 4 and Table II depend entirely on this extraction, the central performance claim is currently unsupported. Please report f_in for each design case, verify the coherence condition, and provide a baseline comparison (e.g., one 12-bit design at the same operating point) showing that the interleaved spectrum yields the same SNDR and SFDR as a full-rate simulation.
  2. [Table II] Table II compares the proposed pre-layout simulation results with measured results from [1] and [2] and post-layout results from [3]. This is not an apples-to-apples comparison: pre-layout simulation omits layout parasitics, process variation, and other post-layout effects that typically degrade SNDR and FoM. The claim of highly competitive performance should therefore either be restricted to a pre-layout comparison with similarly characterized prior work, or be supported by post-layout or measured results for the proposed designs. At minimum, the text should explicitly quantify the expected degradation and avoid presenting pre-layout numbers as directly comparable to silicon-verified entries.
minor comments (5)
  1. [Section I] The sentence 'Concluding remarks are presented in Section IV' should refer to Section V, which contains the conclusions.
  2. [Table I] The inequality direction for the SNDR row is written as '< 6.02N - 4.25 dB', which is inconsistent with Fig. 5 where the specification is 'SNDR > 68 dB'. Please clarify whether the table entry is an upper-bound formula or a design constraint, and make the inequality directions uniform.
  3. [Algorithm 1] The hyperparameters λ, a, δw, ε, w0, and the ANN/DE settings are listed as notes but their numerical values are not reported. Providing the actual values would improve reproducibility and allow readers to assess sensitivity.
  4. [Section III-C] The global optimizer is described as adopting the same components as [10], and two authors of this paper are also authors of [10]. Please state explicitly which components are new to this work (e.g., the specification derivation, the blended local optimizer, or the parallel SNDR method) so that the novelty relative to [10] is clear.
  5. [Section IV] Only one of the 12 design cases is shown in detail, and Fig. 4 plots only SNDR and FoM. A supplementary table listing all design cases with resolution, sampling rate, power, SNDR, SFDR, ENOB, and FoM would make the claim that 'all design cases satisfy the specifications' independently verifiable.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the spec constraints are first-principles noise budgets, and the reported SNDR (72.2 dB) is an independently simulated value that overshoots the derived 68 dB floor, so the result is not forced by construction; the shared-author citation [10] is method inheritance, not load-bearing evidence.

full rationale

The derivation chain is self-contained. Section III-B obtains the SSRE, sampling-error, thermal-noise, and SNDR bounds from a standard quantization-noise budget: equal per-bit error power Δ²/(12N) substituted into Eq. (4) yields Eq. (8), and summing four equal noise powers gives Eq. (11), SNDR < 6.02N − 4.25 dB ≈ 68 dB. These are algebraic derivations, not fits, and the simulated results are not forced by them: Fig. 5 reports an independently simulated SNDR of 72.2 dB against a 68 dB Phase-2 spec, and the Fig. 4 SNDR values spread across designs, so the outcome is not identical to the input by construction. (The Table I inequality direction for the SNDR bound is inconsistent with the reported 72.2 dB, but that is a correctness issue, not a circular one.) The citation to [10], sharing authors Gandara and Liu, supplies the ANN/DE global optimizer whose 'same components' are adopted, but this is implementation inheritance rather than evidence for the conclusion: the central claim rests on Cadence Spectre simulations with a 65-nm PDK, which are externally falsifiable. The Section III-D time-interleaved SNDR extraction is asserted to be 'fast and accurate' without any comparison to a conventional full-rate transient simulation, so the reported SNDR and FoM values rest on an unvalidated measurement method; that is a correctness risk for referees, not a circular reduction, since the SNDR is a measured output rather than an input renamed. No self-definitional, fitted-input, uniqueness-import, or ansatz-smuggling pattern appears.

Assumptions & free parameters 9 free parameters · 7 assumptions · 0 invented entities

The central performance claims rest on a fixed topology, a four-source noise model, the exclusion of capacitor mismatch, and the unvalidated time-interleaved simulation equivalence. Several optimizer hyperparameters (α, λ, a, δw, ε, w, M, convergence thresholds) are chosen by hand or left unspecified, and the global stage is inherited from the self-cited [10], which complicates exact reproduction.

free parameters (9)
  • α (specification scaling factor) = 1 (default); 2 for 2 of 12 cases
    User-set factor that tightens or relaxes all error constraints in Table I; the 12 results depend on its value.
  • λ (expensive-evaluation frequency) = not specified
    Controls how often the expensive full-sine-wave evaluation is run inside Algorithm 1; no numerical value given.
  • a (penalty scale) = not specified
    Scales the rollback penalty in Algorithm 1; no numerical value given.
  • δw (weight update step) = not specified
    Increments the blending weight w after rollback; no numerical value given.
  • ε (termination tolerance) = not specified
    Stops pattern search when step sizes fall below ε; no numerical value given.
  • w0 (initial blend weight) = 0.5
    Initial trust assigned to the cheap-vs-expensive evaluation blend.
  • M (number of interleaved sub-simulations) = not specified (illustration uses 4×4)
    Determines the speedup and phase coverage of the proposed parallel simulation; value is chosen by the user.
  • Global optimizer hyperparameters (DE population, mutation, crossover, ANN architecture, infill batch size) = inherited from [10]
    The global phase reuses the ANN/DE setup of [10], so the present paper does not specify or tune them independently.
  • Frozen-dimension convergence threshold = not specified
    Defines when the global phase declares variables converged and hands off to the local phase.
assumptions (7)
  • standard math Ideal DAC step amplitude ratio A_i/A_{i+1} = 2 and small relative errors δ_i << 1 (Eqs. 2 and 4).
    The SSRE constraint derivation uses first-order Taylor expansion, which requires small δ_i and δ_{i+1}.
  • domain assumption Dynamic errors are uncorrelated across bits.
    Stated after Eq. (4) in Section III-B; used to sum error powers in Eq. (5). Insisted to hold when settling is sufficiently fast.
  • domain assumption Four error sources (quantization, thermal, sampling, settling/SSRE) each contribute LSB^2/12 to total error power.
    Eq. (10) sums four equal powers to get the 6.02N-4.25 dB SNDR bound; this equal split is a budget assumption, not derived from circuit physics.
  • domain assumption Capacitor mismatch is excluded because it is typically calibrated.
    Section II excludes mismatch explicitly; this omits a real performance limiter for high-resolution ADCs.
  • ad hoc to paper Phase-shifted, time-interleaved parallel transient simulations accurately reconstruct full-rate SNDR.
    Proposed in Section III-D without validation against conventional full-sine-wave simulation; all reported SNDR and FoM values depend on this equivalence.
  • domain assumption Fixed topology: bootstrapped switch, dynamic comparator, top-plate sampling Vcm-based binary C-DAC, asynchronous SAR logic.
    Section II fixes the architecture; the optimizer sizes devices only within this topology, limiting the generality claim.
  • domain assumption Only the four listed noise/distortion sources bound performance.
    Eq. (10) ignores comparator metastability, kickback, clock jitter, and other effects; they are assumed negligible.

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Cite this review

Pith. "Pith review of A Global-Local Optimization Approach for Asynchronous SAR ADC Design." pith.science (2026). https://pith.science/paper/62FREGNC

@misc{pith2026250719541,
  author       = {Pith},
  title        = {Pith review of: A Global-Local Optimization Approach for Asynchronous SAR ADC Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/62FREGNC}},
  note         = {Machine review of arXiv:2507.19541}
}
read the original abstract

This paper presents a system-level optimization framework for automated asynchronous SAR ADC design, addressing the limitations of block-level methods in terms of suboptimal performance and manual effort. The proposed approach integrates a fast global optimizer with a multi-fidelity local optimizer to efficiently handle high-dimensionality and expensive simulation cost. Experimental results from 12 design cases, covering 7- and 12-bit resolutions and a frequency range of 100 kHz to 250 MHz, demonstrate highly competitive performance compared with prior works.

Figures

Figures reproduced from arXiv: 2507.19541 by the authors.

Figure 1
Figure 1. The flow diagram of the proposed global-local sizing approach. The [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. The architecture of an N-bit asynchronous SAR ADC. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. SNDR and FoM of 12 design cases: (a) 12 bit (b) 7 bit. 10 design [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (2 more)
Figure 3
Figure 3. Figure 3: Illustration of phase-shifted and time-interleaved parallel transient [PITH_FULL_IMAGE:figures/full_fig_p004_3.png]
Figure 5
Figure 5. Figure 5: Example sizing process for a 12 bit 20 MHz SAR ADC. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

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Reference graph

Works this paper leans on

13 extracted references · 12 canonical work pages · cited by 1 Pith paper

  1. [1]

    write newline

    " write newline "" initialize.prev.this.status FUNCTION begin.bib preamble empty 'skip preamble write newline if " thebibliography " longest.label * " " * write newline " [1] #1 " write newline " url@rmstyle " write newline " " write newline " [2] #2 " write newline " =0pt " write newline " " ALTinterwordstretchfactor * " " * write newline " = 2 plus " wr...

  2. [2]

    o nen c and Pusane, Ali Emre and D \

    11em plus .33em minus .07em 4000 4000 100 4000 4000 500 `\.=1000 = #1 \@IEEEnotcompsoconly \@IEEEcompsoconly #1 * [1] 0pt [0pt][0pt] #1 * \| ** #1 \@IEEEauthorblockNstyle \@IEEEcompsocnotconfonly \@IEEEcompsocconfonly \@IEEEauthorblockAstyle \@IEEEcompsocnotconfonly \@IEEEcompsocconfonly \@IEEEcompsocconfonly \@IEEEauthordefaulttextstyle \@IEEEcompsocnotc...

    work page arXiv 1974

  3. [3]

    Seo, Y.-J

    M.-J. Seo, Y.-J. Roh, D.-J. Chang, W. Kim, Y.-D. Kim, and S.-T. Ryu, ``A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks ,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 1904--1908, Dec. 2018

    work page 1904

  4. [4]

    M. Ding, P. Harpe, G. Chen, B. Busze, Y.-H. Liu, C. Bachmann, K. Philips, and A. van Roermund , ``A Hybrid Design Automation Tool for SAR ADCs in IoT ,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2853--2862, Dec. 2018

    work page 2018

  5. [5]

    M. Liu, X. Tang, K. Zhu, H. Chen, N. Sun, and D. Z. Pan, `` OpenSAR: An Open Source Automated End-to-End SAR ADC Compiler ,'' in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 1em plus 0.5em minus 0.4em Munich, Germany: IEEE, Nov. 2021, pp. 1--9

    work page 2021

  6. [6]

    Huang, J.-M

    C.-P. Huang, J.-M. Lin, Y.-T. Shyu, and S.-J. Chang, ``A Systematic Design Methodology of Asynchronous SAR ADCs ,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1835--1848, May 2016

    work page 2016

  7. [7]

    R. Lyu, Y. Meng, A. Zhao, Z. Bi, K. Zhu, F. Yang, C. Yan, D. Zhou, and X. Zeng, ``A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : ( Invited Paper ),'' in 2024 29th Asia and South Pacific Design Automation Conference ( ASP-DAC ) . 1em plus 0.5em minus 0.4em Incheon, Korea: IEEE, Jan. 2024, pp. 671--678

    work page 2024

  8. [8]

    Zhu, C.-H

    Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, ``A 10-bit 100- MS /s Reference-Free SAR ADC in 90 nm CMOS ,'' IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111--1121, June 2010

    work page 2010

Show all 13 references
  1. [9]

    Shaikh and H

    J. Shaikh and H. Rahaman, ``High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop,'' in 2018 International Symposium on Devices , Circuits and Systems ( ISDCS ) . 1em plus 0.5em minus 0.4em Howrah: IEEE, Mar. 201...

    2018

  2. [10]

    X. Wang, F. Li, and Z. Wang, ``A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs ,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 2838--2842, Dec. 2020

    2020

  3. [11]

    Z. Du, B. Yao, W. Xu, X. Wang, H. Hu, and L. Qiu, ``Capacitor Mismatch Calibration of a 16- Bit SAR ADC Using Optimized Segmentation and Shuffling Scheme ,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 8, pp. 2789--2793, Aug. 2023

    2023

  4. [12]

    A. F. Budak, M. Gandara, W. Shi, D. Z. Pan, N. Sun, and B. Liu, ``An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization ,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1209--1221,...

    2022

  5. [13]

    Moser and R

    I. Moser and R. Chiong, ``A Hooke-Jeeves Based Memetic Algorithm for Solving Dynamic Optimisation Problems ,'' in Hybrid Artificial Intelligence Systems , E. Corchado, X. Wu, E. Oja, \'A . Herrero, and B. Baruque, Eds. 1em plus 0.5em minus 0.4em Berlin, Heidelberg: Springer Be...

    2009

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