Paper Citation Record · LEDGER

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers

As of 19 August 2026, this Paper Citation Record lists 44 of 44 outbound references and 0 inbound Pith citation observations for arXiv:2508.20334.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2508.20334 v1

Coverage vector

measured 44 of 44 reference resolution

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measured 44 of 44 standing notices

One-hop event checks from named stored sources.

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measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

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measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

44 of 44 outbound references displayed

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External citation measurements

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Outbound references

Observation 4012fe98-6dfb-4c38-83ac-2dabe1473b99 · outbound

This paper cites Chatgpt consumes enough power in one year to charge over three million electric cars,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Chatgpt consumes enough power in one year to charge over three million electric cars,

Reference 1

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Observation 211ff7b3-e582-4170-b427-c055c833ed07 · outbound

This paper cites Openai training and inference costs could reach 7bnfor2024,aistartupsettolose 5bn - report,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Openai training and inference costs could reach 7bnfor2024,aistartupsettolose 5bn - report,

Reference 2

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Observation ce3982c6-327a-4182-a64c-00b5e572660e · outbound

This paper cites From words to watts: Benchmarking the energy costs of large language model infer- ence,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers From words to watts: Benchmarking the energy costs of large language model infer- ence,

Reference 3

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This paper cites Beyond Chinchilla-Optimal: Accounting for Inference in Language Model Scaling Laws.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Beyond Chinchilla-Optimal: Accounting for Inference in Language Model Scaling Laws

Reference 4

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Observation cf85c15c-106f-468f-8db9-be1fb634d5a1 · outbound

This paper cites Quantization and training of neural networks for efficient integer-arithmetic-only inference,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Quantization and training of neural networks for efficient integer-arithmetic-only inference,

Reference 5

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Observation 00f5adff-cc76-4e23-8d2a-cf1535564325 · outbound

This paper cites Low-Bit Integerization of Vision Transformers using Operand Reordering for Efficient Hardware.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Low-Bit Integerization of Vision Transformers using Operand Reordering for Efficient Hardware

Reference 6

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Observation ea51733e-f154-4c57-9fb1-98d526b9632e · outbound

This paper cites I-vit: Integer-only quantization for efficient vision transformer inference,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers I-vit: Integer-only quantization for efficient vision transformer inference,

Reference 7

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Observation 9e5e2b9e-f006-4c8a-b611-12ddee52c2fc · outbound

This paper cites Q-ViT: Fully Differentiable Quantization for Vision Transformer.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Q-ViT: Fully Differentiable Quantization for Vision Transformer

Reference 8

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This paper cites Roofline: an insightful visual performance model for multicore architectures,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Roofline: an insightful visual performance model for multicore architectures,

Reference 9

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Observation 1b88ebef-69c1-493b-8df9-ee409956b043 · outbound

This paper cites Thinet: A filter level pruning method for deep neural network compression,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Thinet: A filter level pruning method for deep neural network compression,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:55:20.350079Z

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Observation 2f153c14-7334-4f38-879e-133015956486 · outbound

This paper cites Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding

Reference 11

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Observation 2530407c-6c81-4142-bcbf-d6fedd92c832 · outbound

This paper cites Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1

Reference 12

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Observation 3cbc14cc-3708-4ff0-851f-f9ca6d38125b · outbound

This paper cites Xnor-net: Imagenet classification using binary convolutional neural networks,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Xnor-net: Imagenet classification using binary convolutional neural networks,

Reference 13

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Observation 11afe2ae-df21-496f-950b-4e1b7d4d5157 · outbound

This paper cites Ternary neural networks for resource-efficient ai applications,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Ternary neural networks for resource-efficient ai applications,

Reference 14

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Observation ad4e03be-5286-4e34-990c-3f54e55d96f0 · outbound

This paper cites DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients

Reference 15

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Observation f2e6aaef-203b-407b-b502-75077e8ff345 · outbound

This paper cites Bridging the Accuracy Gap for 2-bit Quantized Neural Networks (QNN).

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Bridging the Accuracy Gap for 2-bit Quantized Neural Networks (QNN)

Reference 16

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Observation 636defa1-b89e-43a2-bca8-4fed6110e090 · outbound

This paper cites FQ-ViT: Post-Training Quantization for Fully Quantized Vision Transformer.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers FQ-ViT: Post-Training Quantization for Fully Quantized Vision Transformer

Reference 17

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Observation a1ef793a-51ad-4659-88d3-936fd4bba2ec · outbound

This paper cites I-bert: Integer-only bert quantization,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers I-bert: Integer-only bert quantization,

Reference 18

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Observation 327c2718-080b-422f-af1b-f80987760fda · outbound

This paper cites An integer- only and group-vector systolic accelerator for efficiently mapping vision transformer on edge,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers An integer- only and group-vector systolic accelerator for efficiently mapping vision transformer on edge,

Reference 19

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Observation 094f6c60-34d1-4e1c-b587-1c8383ae38c2 · outbound

This paper cites Accelerating attention mechanism on fpgas based on efficient reconfigurable systolic array,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Accelerating attention mechanism on fpgas based on efficient reconfigurable systolic array,

Reference 20

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This paper cites Calabash: Accelerating attention using a systolic array chain on fpgas,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Calabash: Accelerating attention using a systolic array chain on fpgas,

Reference 21

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This paper cites A 109-gops/w fpga-based vision transformer accelerator with weight-loop dataflow featuring data reusing and resource saving,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers A 109-gops/w fpga-based vision transformer accelerator with weight-loop dataflow featuring data reusing and resource saving,

Reference 22

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Auto-vit-acc: An fpga- aware automatic acceleration framework for vision transformer with mixed-scheme quantization,

Reference 23

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Me-vit: A single-load memory-efficient fpga accelerator for vision transformers,

Reference 24

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Observation b911fba6-2e80-4c82-bf68-b04dc285fe88 · outbound

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,

Reference 25

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Observation 0895d13d-6dc0-4694-9f7f-f6e066c6250c · outbound

This paper cites An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale

Reference 26

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Training data-efficient image transformers & distillation through attention,

Reference 27

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Observation 71f9fa35-3717-4ad5-bdab-5e58cab6c310 · outbound

This paper cites Fine-grained hardware switching scheme for power reduction in multiplication,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Fine-grained hardware switching scheme for power reduction in multiplication,

Reference 28

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Observation cc44032e-6c27-4fa9-8ba7-5a2642f7ad0e · outbound

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Note on a method for calculating corrected sums of squares and products,

Reference 29

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Ai and memory wall,

Reference 30

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Low power wallace tree multiplier using modified full adder,

Reference 31

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Observation 0926747f-1a82-4bb7-a5c4-e5115cbd5133 · outbound

This paper cites Design and imple- mentation of wallace compressor multiplier using vedic mathematics,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Design and imple- mentation of wallace compressor multiplier using vedic mathematics,

Reference 32

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Observation 176339dc-7070-4237-aa8e-b3db33340092 · outbound

This paper cites Hg-pipe: Vision transformer acceleration with hybrid-grained pipeline,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Hg-pipe: Vision transformer acceleration with hybrid-grained pipeline,

Reference 33

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Observation 0bf6463f-95d0-44ec-8774-7ca82f820993 · outbound

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Refining Datapath for Microscaling ViTs

Reference 34

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Observation 09df1120-c9ae-4bac-b5b1-0ddce17f81c1 · outbound

This paper cites Via: A novel vision-transformer accelerator based on fpga,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Via: A novel vision-transformer accelerator based on fpga,

Reference 35

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Observation 65752d4f-a2c7-4618-8e90-91c579777710 · outbound

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Dfx: A low-latency multi-fpga appliance for accelerating transformer-based text generation,

Reference 36

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This paper cites Adaptable butterfly accelerator for attention-based nns via hardware and algorithm co-design,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Adaptable butterfly accelerator for attention-based nns via hardware and algorithm co-design,

Reference 37

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Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers The annotated transformer,

Reference 38

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This paper cites Heatvit: Hardware-efficient adaptive token pruning for vision transformers,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Heatvit: Hardware-efficient adaptive token pruning for vision transformers,

Reference 39

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This paper cites Hardware accelerator for multi-head attention and position-wise feed-forward in the trans- former,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Hardware accelerator for multi-head attention and position-wise feed-forward in the trans- former,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:55:20.126051Z

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Observation 053d198f-e03a-45d2-850f-09cc1408c307 · outbound

This paper cites Ftrans: energy-efficient acceleration of transformers using fpga,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Ftrans: energy-efficient acceleration of transformers using fpga,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:55:20.114764Z

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Observation 19dd8bec-7419-4b56-bee9-ea3466bc7c29 · outbound

This paper cites Design of ion-implanted mosfet’s with very small physical dimensions,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Design of ion-implanted mosfet’s with very small physical dimensions,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:55:20.102867Z

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Observation 83b2c214-ec39-48d8-b3d2-3127974e990e · outbound

This paper cites Techpowerup,.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Techpowerup,

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:55:20.090716Z

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Observation 82d3a5a9-9ce5-47fe-9c6c-cd5560d59ab9 · outbound

This paper cites Available: https://ietresearch.onlinelibrary.wiley.com/ doi/abs/10.1049/el.2015.3828.

Systolic Array-based Architecture for Low-Bit Integerized Vision Transformers Available: https://ietresearch.onlinelibrary.wiley.com/ doi/abs/10.1049/el.2015.3828

Reference 2016

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-19T06:32:44.657259+00:00.

Pith citing papers

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