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REVIEW 4 major objections 4 minor 63 references

FeynmanDD: Quantum Circuit Analysis with Classical Decision Diagrams

T0 review · 4 major / 4 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read FeynmanDD computes quantum amplitudes by counting solutions on a decision diagram.

desk verdict A real new combination of Feynman path sums and classical BDD counting, with impressive but not yet fully explained speedups; the deferred complexity analysis and missing code keep it conditional. read the letter →

arxiv 2509.08276 v1 pith:67JJMIMV submitted 2025-09-10 quant-ph cs.DS

Ziyuan Wang , Bin Cheng , Longxiang Yuan , Zhengfeng Ji This is my paper · ORCID
classification quant-phcs.DS
keywords FeynmanDDbinarydecisiondiagramsmulti-terminalBDDsum-of-powersrepresentationquantumcircuitsimulationamplitudecomputationequivalencecheckingvariableordering
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

FeynmanDD is a new classical simulation method that turns quantum circuit analysis into a counting problem. The paper shows that, for circuits built from discrete gate sets, the Feynman-path-integral expression for an amplitude can be written as a sum of powers of a root of unity, with the exponent a low-degree multilinear polynomial. That polynomial is compiled into a multi-terminal binary decision diagram, and the amplitude is recovered by counting how many assignments send the polynomial to each residue. The paper proves the evaluation runs in time linear in the diagram size, and reports that for structured families such as GHZ, BV, linear-network, and supremacy-benchmark circuits, the diagrams stay small enough to beat standard simulators by orders of magnitude. A reader should care because this opens a new route to classically simulating and verifying quantum circuits that exploits repetition in the circuit's algebraic form rather than in its state vector.

What carries the argument

The load-bearing object is the sum-of-powers form: a circuit gate is encoded as a power ω^{ℓ(x)} of a root of unity, so the whole circuit becomes a uniformly normalized sum over internal wire values, with the exponent a multilinear polynomial. The companion machinery is the multi-terminal binary decision diagram, a rooted directed acyclic graph whose leaves hold residue values, built for the exponent polynomial. Once the MTBDD exists, evaluation of the sum-of-powers form is a residue-counting problem: count assignments yielding each residue and combine with the roots of unity, in time linear in the diagram size. Two ordering choices carry the method: the order in which polynomial terms are a

What would settle it

Instrument the implementation to record the MTBDD node count B(f) and runtime for amplitudes on the published benchmark circuits; if runtime is not proportional to B(f) up to the counting bit length, the claimed linear-in-B(f) guarantee is not what the implementation delivers. Alternatively, run it on random layers of CCZ gates and check whether the diagram size and runtime grow exponentially with qubit count despite trying each ordering heuristic the paper suggests; that would demarcate the method's practical boundary.

Watch

Extended reading notes

Core claim

The central claim is that one can map a quantum circuit to a sum-of-powers representation of the target amplitude—an expression 1/√R Σ_y ω^{f(x,y)} where ω is a root of unity and f is a multilinear polynomial of degree at most three—and then treat the circuit-analysis task as a counting problem over f. Given an MTBDD for f with B(f) nodes, FeynmanDD computes any amplitude exactly in O(mB(f)) time, where m is the counting bit length; the same machinery handles acceptance probabilities and, by forming the trace of U†V, equivalence checking. The paper constructs sum-of-powers forms for three universal gate sets—the H/Z/CZ/CCZ set, the Clifford+T set, and the supremacy-benchmark gate set—and pro

Load-bearing premise

The method's speed collapses if the circuit's exponent polynomial cannot be squeezed into a small decision diagram; the paper's experiments depend on variable-ordering heuristics to keep the diagram small, and it defers a formal characterization of when that is possible.

Editorial extensions

If this is right

  • Single-amplitude simulation becomes as easy as the diagram is small: any circuit whose sum-of-powers polynomial admits a polynomially sized MTBDD is simulable in polynomial time, independent of entanglement structure.
  • Sampling by sequential conditional probabilities is available on the same diagram, with a quadratic cost in diagram size, so structured circuits can be sampled without storing the full state.
  • Equivalence checking can be done exactly via the trace criterion, using the same counting engine, and the paper reports fast checks on large GHZ and BV circuits.
  • Adding a new gate set requires only a configuration-file entry for the gate's power form, not a new data structure, so the method extends to other discrete universal sets.
  • The existence of a circuit family where FeynmanDD is efficient while tensor-network and Clifford methods are provably costly suggests BDD counting captures structure those methods miss.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: if polynomially sized sum-of-powers BDDs exist for a broad class of circuits, the method effectively characterizes a new classical-simulability region defined by low XOR-treewidth of the path-sum polynomial, rather than by stabilizer rank or tensor-network cutwidth.
  • Editorial inference: the variable-ordering bottleneck suggests a direct test: run FeynmanDD on random constant-depth IQP circuits with many CCZ gates under sifting and tensor-order heuristics; if diagrams blow up polynomially with qubit count, the practical reach extends well beyond the tested families.
  • Editorial inference: the trace-based equivalence check could be combined with circuit optimizers to validate whole compiled programs exactly; a concrete extension is to benchmark on large Clifford+T circuits produced by rotation synthesis, where the paper only sketches the expected BDD behavior.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper proposes FeynmanDD, a decision-diagram method for exact simulation and equivalence checking of quantum circuits over discrete gate sets. The method derives a sum-of-powers (SOP) representation of an amplitude or trace, converts the associated multilinear polynomial over Z_r into an MTBDD, and evaluates the amplitude by counting how many assignments map to each residue. Sections 3--4 give the SOP calculus for gate sets Z, T, and the Google-supremacy set G, including contraction and substitution operations. Section 5 describes a binary synthesis construction and variable-ordering heuristics. Section 6 gives formulas for amplitudes, probabilities, sampling, and equivalence checking via tr(U_C0^dag U_C1). Section 7 reports speedups over DDSIM, SliQSim, and WCFLOBDD on Google-supremacy, GHZ, BV, and especially 'linear-network' circuits; Section 8 compares equivalence checking with MQT-QCEC. The paper states that amplitude simulation is linear in B(f), where B(f) is the MTBDD size, but explicitly defers a formal complexity characterization of the linear-network family to future work.

Significance. If the claimed runtime bounds held with polynomial B(f) for the tested families, FeynmanDD would be a genuinely interesting bridge between BDD counting and Feynman-path simulation: it would enable exact single-amplitude computation, exact sampling, and exact equivalence checking with very small memory on structured circuits. The SOP framework is flexible, the counting formulation is exact, and the paper gives clear Theorems 1--2 and explicit formulas in Section 6. These are strengths. However, the submitted manuscript does not prove that B(f) stays small for the headline families, and the only justification for the MTBDD-building phase is empirical ('numerical simulations suggest'). The significance is therefore conditional on the deferred complexity analysis and on the reproducibility of the experimental results. No machine-checked proofs or released code accompany the paper, so the empirical claims are not independently verifiable at this stage.

major comments (4)
  1. [§6.1 and §5] The claim 'our simulation algorithm achieves runtime linear in B(f)' is only established for the counting phase. The BDD construction, which Section 5 calls 'the most computationally expensive step', is justified by 'Numerical simulations suggest' for the binary synthesis method, with no bound on its time relative to B(f); variable ordering can change B(f) exponentially. Therefore the full pipeline's runtime is not shown to be linear in B(f). Please either provide a construction-time bound or restrict the claim to the counting stage and report construction versus counting times in the experiments.
  2. [§1, §7.3] The formal complexity of the method, and specifically of the linear-network family, is explicitly deferred: §1 says 'In a follow-up work, we will provide a characterization of the complexity', and §7.3 says 'A more comprehensive analysis of this circuit family will be presented in subsequent work.' Yet the linear-network circuits are 'purposefully' designed so that the number of forward signals is bounded by k+1. As submitted there is no theorem showing B(f) is polynomial for this family, so the extreme speedups in Table 6 are unexplained empirically; they could depend on the fixed qubit ordering. A scaling experiment in n and k with several orderings, or an actual theorem, is needed to support the claimed advantage over tensor-network and Clifford methods.
  3. [§5 and §7] The experimental protocol fixes the 'qubit order' variable ordering for all circuits. Section 5 states that variable ordering 'may significantly impact the final size' and exhibits an ordering that makes the Hadamard-chain BDD blow up exponentially. For the Google-supremacy results (Tables 2--3), no evidence is given that the speedups are robust with respect to variable ordering or circuit variation (e.g., neighboring grid sizes). Without this, the 0.01--0.2 s amplitude times could be artifacts of a single favorable ordering rather than a property of the circuits. Report results for at least two orderings, or provide a size analysis of B(f) for these circuits.
  4. [§7 (experimental setup)] No code, data, or detailed benchmark-generation scripts are released. Given that the performance claims rely entirely on the experimental tables, the absence of artifacts prevents independent reproduction. I ask the authors to release the FeynmanDD implementation, the exact circuit instances (including random seeds for GRCS and linear-network circuits), and the scripts used for the DDSIM/SliQSim/WCFLOBDD comparisons.
minor comments (4)
  1. [§6.1] The symbol m is used for the number of circuit gates earlier and for the bit length of the counting result in Section 6.1. Use different symbols (e.g., M for gate count, ℓ for bit length) to avoid confusion.
  2. [§5] The counting-identity paragraph contains a garbled phrase: 'when a variable x appears exactly twice in the terms having form r/2 x x0 and r/2 x x1'. Please rewrite the condition precisely (which monomials, which coefficients, and what simplification follows).
  3. [Tables 4--5] Typographical errors: 'meausred' for 'measured' in the captions of Tables 4 and 5. Also, the notation in Table 3's caption '(x)' should be explained more clearly in the table text.
  4. [§6.2] The equivalence criterion is stated as 'equivalent (up to a global phase)' when the trace has unit norm. Please spell out the argument briefly (all eigenvalues of a unitary are on the unit circle, so modulus 2^n forces them to coincide), and clarify the distinction between 'equal as unitaries' and 'equal up to a global phase'.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the runtime claim follows from standard BDD counting, and the deferred BDD-size characterization is an open-evidence gap, not a circular step.

full rationale

FeynmanDD's derivation chain is self-contained. The sum-of-powers (SOP) representation (Theorem 1) is constructed directly from gate matrix elements and the Feynman path sum; it does not presuppose the amplitudes or counts that the algorithm later outputs. Section 6.1's linear-in-B(f) runtime claim is a direct application of known BDD model-counting results (Knuth [31]; Wegener [58]): once f is represented as an MTBDD of size B(f), the counts N_j are obtained by counting paths, not by fitting any parameter to the target amplitude. No benchmark output is used to define the method, and no load-bearing conclusion rests on a self-citation. The experimental speedups are conditional on B(f) remaining small under the chosen qubit order; the paper explicitly flags this as an open question ('the tensor contraction complexity bound is an upper bound that may be very loose in certain cases', Section 5; 'A more comprehensive analysis of this circuit family will be presented in subsequent work', Section 7.3; 'In a follow-up work, we will provide a characterization of the complexity of the FeynmanDD method', Section 1). That is an unproven premise or evidence gap, not a circular reduction: the theoretical claim is conditional on B(f), and the empirical claims are observations on particular circuit families. The equivalence-checking criterion tr(U†V)=2^n ω^j is a standard mathematical fact, and the benchmarks (GRCS, RevLib, and the authors' own circuit families) are test inputs, not fitted parameters. No circular step can be exhibited from the paper's equations or citations, so the score is 0.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

No free parameters are fitted to data; the algorithm relies on standard BDD counting, explicit power-form gate representations, and the trace criterion. No new physical entities are introduced.

assumptions (3)
  • standard math BDD counting algorithms compute the number of satisfying assignments in time linear in BDD size (Knuth TAOCP; Wegener).
    Section 2.3 and 6.1 rely on this to turn MTBDD into counts N_j.
  • domain assumption Gate sets Z, T, G admit sum-of-powers representations with roots of unity, e.g., H = sum over x,y of (-1)^{xy}/sqrt(2).
    Section 3 builds SOP forms on these explicit representations; Theorem 1 is summarized without full proof but follows by construction from the gate definitions.
  • standard math Two unitaries U and V are equivalent up to global phase iff tr(U^dag V) has magnitude 2^n.
    Section 6.2 reduces equivalence checking to evaluating this trace, relying on spectral properties of unitary matrices.

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Cite this review

Pith. "Pith review of FeynmanDD: Quantum Circuit Analysis with Classical Decision Diagrams." pith.science (2026). https://pith.science/paper/67JJMIMV

@misc{pith2026250908276,
  author       = {Pith},
  title        = {Pith review of: FeynmanDD: Quantum Circuit Analysis with Classical Decision Diagrams},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/67JJMIMV}},
  note         = {Machine review of arXiv:2509.08276}
}
read the original abstract

Applications of decision diagrams in quantum circuit analysis have been an active research area. Our work introduces FeynmanDD, a new method utilizing standard and multi-terminal decision diagrams for quantum circuit simulation and equivalence checking. Unlike previous approaches that exploit patterns in quantum states and operators, our method explores useful structures in the path integral formulation, essentially transforming the analysis into a counting problem. The method then employs efficient counting algorithms using decision diagrams as its underlying computational engine. Through comprehensive theoretical analysis and numerical experiments, we demonstrate FeynmanDD's capabilities and limitations in quantum circuit analysis, highlighting the value of this new BDD-based approach.

Figures

Figures reproduced from arXiv: 2509.08276 by the authors.

Figure 1
Figure 1. Left: Variable labeling for a quantum circuit of gates from gate set Z. Right: A decomposition that derives a power-of-sum representation for CNOT. The H gate has matrix entries (−1)xy/ √ 2 where x and y are the variables for the input and output wires respectively. The CCZ gate has diagonal entries of (−1)x1x2x3 with 0 entries elsewhere, using the same set of variables for the input and output to indicate its diago… view at source ↗
Figure 2
Figure 2. BDD for the reduced func￾tion x4 + x5x6 + x4x6x7. For instance, in the example circuit on the left part of [PITH_FULL_IMAGE:figures/full_fig_p011_2.png] view at source ↗

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Pith tools

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