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Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices

T0 review · 2 major / 5 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read Conveyor-belt electron shuttling in silicon-oxide devices is robust above a clavier-gate voltage of about 150 mV, but positively charged interface defects can permanently capture the electron at lower voltages.

desk verdict Solid, useful 3D shuttling simulations with a believable low-voltage mode transition; the permanent-capture claim for positive defects rests on a static-charge model the paper itself contradicts. read the letter →

arxiv 2512.03853 v3 pith:HFTPFD26 submitted 2025-12-03 quant-ph cond-mat.mes-hall

Jack J. Turner , Christian W. Binder , Guido Burkard , Andrew J. Fisher This is my paper · ORCID
classification quant-phcond-mat.mes-hall PACS 85.35.Gv73.63.Hs
keywords electronshuttlingSiMOSsiliconspinqubitschargedefectsconveyor-belttransportLandau-Zenertransitionsquantumdotarraydevicesimulation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper attempts to establish the operating conditions under which conveyor-belt electron shuttling — moving a single electron along a chain of gates by smoothly sliding its confining potential — works reliably in silicon-oxide (SiMOS) devices, a technology relevant for scalable quantum computers. Using full three-dimensional simulations that solve the electrostatic potential and the time-dependent Schrödinger equation together, the authors show that at low gate voltage (around 100 millivolts) the shuttling collapses into a bucket-brigade mode that badly excites the electron, because extra oxide screening under some gates weakens the confinement. Above about 150 millivolts, shuttling is restored and is robust against realistic interface roughness, gate misalignments, and defects buried in the oxide. The main remaining threat is a positively charged defect at the silicon/oxide interface, which at low voltages can permanently capture the electron. The paper concludes with concrete voltage windows and identifies positive-interface defects as the obstacle that fabrication should target.

What carries the argument

The key machinery is the instantaneous eigenenergy spectrum of the moving dot, analysed through the Landau–Zener formula P_D = exp(-2π a²/(ℏ|α|)), where a is the gap between neighbouring orbital levels and α the sweep rate. The paper shows how the multi-layer gate stack's uneven screening shrinks a under alternating gates at low voltage, driving the shuttling through avoided crossings and into a bucket-brigade mode; this same gap analysis explains robustness at higher voltage and the trapping by positive defects, whose bound states sit deep below the conveyor levels. On the simulation side, the spectral projection method propagates the wavefunction by projecting onto the instantaneous eigenb

What would settle it

Measure shuttling fidelity across a single SiMOS device with a deliberately placed or identified positive interface trap while sweeping the clavier voltage; if at Vc ≈ 100 mV the electron does not remain trapped for the remainder of the cycle (e.g., escapes after the trap neutralises), the fixed-charge capture scenario is refuted. Alternatively, a self-consistent Schrödinger-Poisson simulation with occupation-dependent trap charge would show capture without permanent trapping.

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Extended reading notes

Core claim

The central claim is that the viability of conveyor-belt electron shuttling in SiMOS devices is governed by a sharp voltage threshold set by the multi-layer gate stack. Because the clavier gates sit in two different oxide layers, the lower-layer gates are screened more heavily; below about 100 mV this creates barriers under alternating gates, and the electron hops rather than rides, suffering large orbital excitation. Raising the clavier voltage above roughly 150 mV re-opens the orbital energy gaps and makes the transport adiabatic and loss-free, with ground-state fidelities above 99% for interface roughness up to 0.9 nm RMS and gate misalignments up to 30%. Negatively charged defects only d

Load-bearing premise

The simulations treat every defect as a point charge of fixed magnitude +e or -e whose charge does not change when it absorbs or emits an electron; if real interface traps neutralise upon capturing an electron, the predicted permanent capture and worst-case excitation results could be substantially weaker.

Editorial extensions

If this is right

  • SiMOS conveyor-belt shuttling should be operated with clavier-gate voltages above about 150 mV (and below the very high range where excessive confinement causes excitation) to remain adiabatic.
  • Interface roughness and gate misalignment at realistic levels (RMS ≤ 0.9 nm; misalignment ≤ 30%) do not break shuttling, so fabrication tolerances can be looser than feared.
  • Positively charged interface defects are the primary showstopper: at low bias they can permanently trap the electron, so device designs or passivation processes should target donor-like interface traps.
  • Negatively charged defects are comparatively benign at proper operating voltages, causing negligible charge loss and fidelities of roughly 99–99.99%.
  • Even when the electron escapes a positive defect, the resulting orbital excitation may open spin-flip channels, but the small spin-orbit admixture (≈10⁻³) keeps spin-conserving decay dominant.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the fixed-charge assumption were relaxed, the permanent-capture conclusion could weaken: real Si/SiO2 interface traps (Pb centers) are amphoteric and would neutralise after capturing an electron, potentially releasing it and restoring shuttling.
  • The sharp fidelity drop at the conveyor-belt–bucket-brigade transition could serve as a sensitive experimental probe of the effective screening depth in the gate stack, without requiring single-defect resolution.
  • The voltage-window result suggests a practical tuning strategy: sweep the clavier voltage while measuring shuttling fidelity to locate the onset above ~150 mV and to detect strong positive traps via the capture signature.
  • The orbital-only model sets a necessary-but-not-sufficient condition for spin qubit transport; adding spin and valley dynamics would test whether the identified safe windows survive phonon-mediated spin relaxation in the excited orbitals.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. This paper presents full 3D simulations of conveyor-belt electron shuttling in a SiMOS device, solving the Poisson equation for the gate-induced potential and the time-dependent Schrödinger equation for the electron. The authors study the effect of clavier-gate voltage, shuttling speed, interface roughness, gate misalignment, and isolated charge defects. Their central findings are: (i) at low clavier voltage (~100 mV), the multilayer gate geometry causes a transition from conveyor-belt to bucket-brigade shuttling with strong orbital excitation; (ii) raising the voltage above ~150 mV restores conveyor-belt operation, which is robust to realistic interface roughness and gate misalignment; and (iii) positive charge defects at the Si/SiO2 interface are the dominant obstacle, capable of permanently capturing the electron at low voltages. The numerical method is a spectral projection scheme validated against split-operator evolution, and the model parameters are taken from prior literature rather than fitted.

Significance. If the conclusions hold, the paper provides a valuable design-oriented map of operating regimes for SiMOS shuttling, a topic where experiments are still emerging. The study's strengths are the full 3D treatment, the absence of fitted parameters targeting the results, the clear benchmark of the spectral projection method (Appendix B2d), and the systematic parameter sweeps. However, the most distinctive claim—that positive interface defects can permanently trap the shuttled electron—rests on a fixed point-charge defect model that is in tension with the amphoteric Pb-center physics described in the paper's own introduction. Because this issue directly affects the headline threat ranking, the central conclusion is not yet secure without additional analysis or a explicit limitation-aware bounding study.

major comments (2)
  1. [Sec. II.C, Eq. (5); Sec. III.D.2, Fig. 13] The positive-defect simulations model each defect as a fixed point charge q=+e. The introduction states that interface traps are amphoteric Pb0/Pb1 centers whose charge state depends on occupancy. Under this physical picture, a +e trap that captures the shuttled electron should neutralize or at least change its charge state, removing the ~200 meV static well that is invoked to explain 'permanent' trapping. The reported permanent capture and the ranking 'positive defects are the greatest obstacle' may therefore be an artifact of the frozen charge state. A concrete bounding test is needed—for example, turning off the trap charge after the first capture event, or using an occupation-dependent defect charge—and the resulting changes in PL and fidelity should be reported. Without such a test, the central conclusion of Sec. III.D.2 is not supported.
  2. [Sec. III.B, Figs. 4 and 6] The roughness study appears to use a single stochastically generated interface realization per RMS value. Since interface roughness is a random field, a single realization cannot support quantitative statements such as 'ground state fidelities stay above 99% even with roughness as high as RMS=0.9 nm'. The authors should either average over an ensemble of roughness realizations for each RMS or state explicitly that the reported results are single-sample evidence. This is important because the robustness claim for roughness is a central positive result of the paper.
minor comments (5)
  1. [Fig. 14 caption] The caption says 'Vs = 500mV', 'Vs = 250mV', and 'Vs = 100mV' in the three panels; these should be Vc (clavier voltage) for consistency with the text.
  2. [Fig. 4 caption] The cross-reference 'Fig. Ie' should be 'Fig. 1e'.
  3. [Sec. II.D and Appendix B2b] 'Lanzcos' is a misspelling of 'Lanczos'. Also, the effective-mass tensor notation in Eq. (9) could be clarified by explicitly defining m_t and m_l immediately after the equation.
  4. [Sec. III.D.2 and Sec. IV] The word 'excitement' is used where 'excitation' is intended in several places (e.g., 'only minor excitement occurs').
  5. [Eq. (12) and Appendix A] The Landau-Zener formula is used repeatedly but no reference or derivation is given for the specific form with exponent a^2/(ℏ|α|). A brief citation or a note on the sign convention for α would help the reader.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the central claims emerge from solving the stated 3D Poisson + time-dependent Schrödinger equations with independently sourced parameters; the one overlapping-author citation is contextual, not load-bearing.

full rationale

The paper's predictions are outputs of a well-specified numerical model, not identities with its inputs. The potential is assembled from stated ingredients: the gate voltages of Eq. (1), the oxide barrier of Eq. (6), and point-charge defects of Eq. (5); the dynamics are then computed with the Schrödinger equation, Eqs. (8)-(9). The swept parameters Vc, Vs, and v are independent control variables, and no parameter is fitted to the reported fidelities, charge-loss probabilities, or the Vc ≈ 100 mV conveyor-to-bucket-brigade transition. The Landau-Zener formula, Eq. (12), is used after the fact to interpret the observed avoided crossings and is not used to set the thresholds. The numerical solver is independently validated against a split-operator Trotter benchmark (Appendix B2d, Fig. 15) and its equivalence to exact Schrödinger evolution is derived in Appendix C, so the spectral projection method is not circularly relied upon. The only overlapping-author citation is [16] (Jeon, Benjamin, Fisher), which is cited as prior 2D context; the present paper independently simulates negative defects in 3D in Sec. III.D.1, so that citation is not load-bearing. The fixed +e point-charge trap model, Sec. II.C and Eq. (5), is a physical simplification that may affect the correctness of the permanent-capture claim, but that is a modelling assumption and a correctness risk, not a circularity: the conclusion is not definitionally identical to the input but is a computed consequence of that stated assumption.

Assumptions & free parameters 4 free parameters · 6 assumptions · 0 invented entities

No new physical entities are postulated; defects, roughness, and gate misalignment are empirically known device features. The load-bearing choices are the anisotropic single-valley effective mass, static point-charge defects, the fixed multi-layer geometry, and periodic boundary conditions. The main hand-set inputs are H=0.3, the 3000 meV oxide barrier, and the unstated roughness correlation-length cutoff.

free parameters (4)
  • Hurst coefficient H = 0.3
    Sets the roughness PSD exponent 2(1+H) (Eq. 4); taken from Jacobs et al. [60] and fixed for all roughness runs.
  • Si/SiO2 conduction-band offset = 3000 meV
    Oxide potential step (Eq. 6); a standard literature value but hand-set, and sensitivity of the shuttling results to it was not swept.
  • Roughness correlation length / PSD cutoffs = not stated
    The power-law PSD (Eq. 4) requires low- and high-q cutoffs and a normalization protocol beyond target RMS; these are not specified in Sec. II.B and could affect the roughness-robustness conclusions.
  • Gate-stack geometry (oxide spacings) = 15 nm under side-gates, 5 nm inter-layer
    Device dimensions from fabrication practice [55]; the multi-layer screening collapse (Sec. III.A) is driven by the extra 5 nm of oxide under layer-3 gates, so the central result depends on this hand-chosen geometry.
assumptions (6)
  • domain assumption Anisotropic single-valley effective-mass Hamiltonian (Eq. 9) with mt=0.190me and ml=0.916me captures the electron dynamics
    All Schrödinger evolution uses this; valley splitting and spin are explicitly excluded (Sec. II.D and Conclusions) even though interface roughness is known to affect valley physics.
  • domain assumption Defects are static point charges ±e entering only through Vch in Eq. (5); no charge-state dynamics and no dynamical screening
    Underlies the positive-defect capture result in Sec. III.D.2; real Pb centers are amphoteric (Sec. I), so occupancy would change on capture.
  • domain assumption The electron exerts no back-action on the potential: one-way coupling of the Poisson solution into the Schrödinger dynamics
    V(r,t) is fixed by gates and static charges (Eqs. 5-7); there is no self-consistent Poisson-Schrödinger update during shuttling.
  • domain assumption Periodic boundary conditions in the shuttling direction
    One 140 nm unit cell is used with PBC (Figs. 5, 8); every defect repeats every 140 nm, so capture and excitation effects include the periodic images of the same trap.
  • standard math Landau-Zener formula PD=exp(-2πΓ) (Eq. 12) governs excitation probabilities at avoided crossings
    Used to interpret the sharp conveyor-to-bucket-brigade onset and the voltage-dependent fidelity minimum; a standard two-level result applied heuristically.
  • domain assumption The multi-layer gate stack with 5 nm extra oxide under layer-3 gates is representative of realistic SiMOS fabrication
    The central low-voltage collapse (Sec. III.A) is a direct consequence of this geometry; a single-layer gate stack would not exhibit it.

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Pith. "Pith review of Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices." pith.science (2026). https://pith.science/paper/HFTPFD26

@misc{pith2026251203853,
  author       = {Pith},
  title        = {Pith review of: Modelling the Impact of Device Imperfections on Electron Shuttling in SiMOS devices},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HFTPFD26}},
  note         = {Machine review of arXiv:2512.03853}
}
read the original abstract

Extensive theoretical and experimental work has established high-fidelity electron shuttling in Si/SiGe systems, whereas demonstrations in Si/SiO2 (SiMOS) remain at an early stage. To help address this, we perform full 3D simulations of conveyor-belt charge shuttling in a realistic SiMOS device, building on earlier 2D modelling. We solve the Poisson and time-dependent Schrodinger equations for varying shuttling speeds and gate voltages, focusing on potential pitfalls of typical SiMOS devices such as oxide-interface roughness, gate fabrication imperfections, and charge defects along the transport path. The simulations reveal that for low clavier-gate voltages, the additional oxide screening in multi-layer gate architectures causes conveyor-belt shuttling to collapse to the bucket-brigade mode, inducing considerable orbital excitation in the process. Increasing the confinement restores conveyor-belt operation, which we find to be robust against interface roughness, gate misalignment, and charge defects buried in the oxide. However, our results indicate that defects located at the Si/SiO2-interface can induce considerable orbital excitation. For lower conveyor gate biases, positive defects in the transport channel can even capture passing electrons. Hence we identify key challenges and find operating regimes for reliable charge transport in SiMOS architectures.

Figures

Figures reproduced from arXiv: 2512.03853 by the authors.

Figure 1
Figure 1. FIG. 1. (a) Schematic of a typical quantum dot array structure used for shuttling with clavier-gates [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. (a) The orbital ground state infidelity at the end of the shuttling down the channel for different [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. Snapshots from 3D simulations of shuttling 20 m/s along a flat interface with [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (10 more)
Figure 4
Figure 4. Figure 4: FIG. 4. Interface topography of the simulated quan [PITH_FULL_IMAGE:figures/full_fig_p008_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. Snapshots of electron charge density from 3D simulations of shuttling an electron down the channel [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6. The orbital ground state infidelity at the end of the shuttling down the channel for different RMS [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7. The orbital ground state infidelity at the end of shuttling in the x-direction at 100 m/s for different [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 9
Figure 9. Figure 9: FIG. 9. The orbital ground state infidelity at the [PITH_FULL_IMAGE:figures/full_fig_p011_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10. Orbital ground state infidelity at the end of shuttling with a negatively charged interface defect [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11. Snapshots from 3D simulations of shut [PITH_FULL_IMAGE:figures/full_fig_p013_11.png]
Figure 13
Figure 13. Figure 13: FIG. 13. Charge loss probability (top panels) and orbital ground state infidelity (bottom panels) for [PITH_FULL_IMAGE:figures/full_fig_p014_13.png]
Figure 14
Figure 14. Figure 14: FIG. 14. The 10 lowest instantaneous eigenenergies of the system potential plotted as a function of time [PITH_FULL_IMAGE:figures/full_fig_p020_14.png]
Figure 15
Figure 15. Figure 15: FIG. 15. Evolution of squared level coefficients [PITH_FULL_IMAGE:figures/full_fig_p023_15.png]

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